From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751501AbeECJ0E (ORCPT ); Thu, 3 May 2018 05:26:04 -0400 Received: from mail-bl2nam02on0081.outbound.protection.outlook.com ([104.47.38.81]:47159 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750898AbeECJZ7 (ORCPT ); Thu, 3 May 2018 05:25:59 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Tejas Patel To: , CC: , , Tejas Patel Subject: [PATCH] clk: divider: Use round off divisor instead of round up Date: Thu, 3 May 2018 02:25:35 -0700 Message-ID: <1525339535-25595-1-git-send-email-tejas.patel@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(39380400002)(39850400004)(376002)(346002)(396003)(2980300002)(438002)(189003)(199004)(478600001)(126002)(336012)(110136005)(426003)(50466002)(106002)(48376002)(54906003)(36386004)(9786002)(486006)(2616005)(4326008)(476003)(107886003)(8746002)(81166006)(81156014)(8936002)(356003)(6666003)(50226002)(2906002)(186003)(8676002)(63266004)(44832011)(1857600001)(305945005)(47776003)(77096007)(36756003)(72206003)(5660300001)(106466001)(316002)(51416003)(26005)(7696005)(59450400001)(5890100001)(107986001);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1PR02MB1676;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; 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So even though actual divisor is closer to round down integer value it will return round up integer value. This can result into large variation between expected clock rate and actual clock rate. See for example: Parent rate is 1400MHz and desired child rate is 693MHz. So if we calculate simple divisor for child clock it would be 1400000000/693000000 = 2.02. But, because of roundup logic (DIV_ROUND_UP_ULL(1400000000, 693000000)) divisor returned from divider_get_val() will be 3. So actual child rate would be (1400000000/3) = 466666667 instead of 693000000. Here, difference between expected child rate and actual child rate is approx 226MHz. So there is almost 32% error between desired and actual clock rate. Fix this by using round off value (DIV_ROUND_CLOSEST_ULL) instead of round up/down. Signed-off-by: Tejas Patel --- drivers/clk/clk-divider.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index b6234a5..6ae6d43 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -391,7 +391,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate, { unsigned int div, value; - div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + div = DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate); if (!_is_valid_div(table, div, flags)) return -EINVAL; -- 2.7.4 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.