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Thu, 07 Jun 2018 05:12:07 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1fQtlq-0001FQ-GZ; Thu, 07 Jun 2018 05:12:02 -0700 Received: from xsj-pvapsmtp01 (xsj-pvapsmtp01.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w57CBuS6006539; Thu, 7 Jun 2018 05:11:56 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1fQtlk-0001EO-4B; Thu, 07 Jun 2018 05:11:56 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id 4256D1214C7; Thu, 7 Jun 2018 17:41:55 +0530 (IST) From: Manish Narani To: , , , , , , , , , , , , CC: Manish Narani Subject: [RFC PATCH 1/3] arm64: zynqmp: dt: Add support for setting SD tap delays Date: Thu, 7 Jun 2018 17:41:38 +0530 Message-ID: <1528373500-24663-1-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(396003)(39380400002)(39860400002)(346002)(376002)(2980300002)(438002)(189003)(199004)(36756003)(186003)(103686004)(107886003)(6266002)(478600001)(72206003)(44832011)(50466002)(52956003)(2616005)(486006)(90966002)(48376002)(26005)(426003)(476003)(2906002)(2201001)(126002)(36386004)(7416002)(106002)(5660300001)(51416003)(81156014)(5890100001)(356003)(6666003)(8936002)(8746002)(63266004)(8676002)(106466001)(59450400001)(81166006)(4326008)(42186006)(336012)(110136005)(305945005)(316002)(50226002)(47776003)(107986001)(921003)(1121003)(2101003)(83996005)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:BN6PR02MB2354;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; 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Earlier, these tap values were made static via macros in the driver. So changing the tap values in the device tree makes the driver free from handling different tap values inside it. Signed-off-by: Manish Narani --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 40 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/x= ilinx/zynqmp.dtsi index a091e6f..696aac8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -491,6 +491,26 @@ interrupts =3D <0 48 4>; reg =3D <0x0 0xff160000 0x0 0x1000>; clock-names =3D "clk_xin", "clk_ahb"; + xlnx,itap_delay_sd_hsd =3D <0x15>; + xlnx,otap_delay_sd_hsd =3D <0x5>; + xlnx,itap_delay_sdr25 =3D <0x15>; + xlnx,otap_delay_sdr25 =3D <0x5>; + xlnx,itap_delay_sdr50 =3D <0>; + xlnx,otap_delay_sdr50 =3D <0x3>; + xlnx,itap_delay_sd_ddr50 =3D <0x3D>; + xlnx,otap_delay_sd_ddr50 =3D <0x4>; + xlnx,itap_delay_mmc_hsd =3D <0x15>; + xlnx,otap_delay_mmc_hsd =3D <0x6>; + xlnx,itap_delay_mmc_ddr50 =3D <0x12>; + xlnx,otap_delay_mmc_ddr50 =3D <0x6>; + xlnx,itap_delay_sdr104_b0 =3D <0>; + xlnx,otap_delay_sdr104_b0 =3D <0x3>; + xlnx,itap_delay_sdr104_b2 =3D <0>; + xlnx,otap_delay_sdr104_b2 =3D <0x2>; + xlnx,itap_delay_mmc_hs200_b0 =3D <0>; + xlnx,otap_delay_mmc_hs200_b0 =3D <0x3>; + xlnx,itap_delay_mmc_hs200_b2 =3D <0>; + xlnx,otap_delay_mmc_hs200_b2 =3D <0x2>; }; sdhci1: sdhci@ff170000 { @@ -500,6 +520,26 @@ interrupts =3D <0 49 4>; reg =3D <0x0 0xff170000 0x0 0x1000>; clock-names =3D "clk_xin", "clk_ahb"; + xlnx,itap_delay_sd_hsd =3D <0x15>; + xlnx,otap_delay_sd_hsd =3D <0x5>; + xlnx,itap_delay_sdr25 =3D <0x15>; + xlnx,otap_delay_sdr25 =3D <0x5>; + xlnx,itap_delay_sdr50 =3D <0>; + xlnx,otap_delay_sdr50 =3D <0x3>; + xlnx,itap_delay_sd_ddr50 =3D <0x3D>; + xlnx,otap_delay_sd_ddr50 =3D <0x4>; + xlnx,itap_delay_mmc_hsd =3D <0x15>; + xlnx,otap_delay_mmc_hsd =3D <0x6>; + xlnx,itap_delay_mmc_ddr50 =3D <0x12>; + xlnx,otap_delay_mmc_ddr50 =3D <0x6>; + xlnx,itap_delay_sdr104_b0 =3D <0>; + xlnx,otap_delay_sdr104_b0 =3D <0x3>; + xlnx,itap_delay_sdr104_b2 =3D <0>; + xlnx,otap_delay_sdr104_b2 =3D <0x2>; + xlnx,itap_delay_mmc_hs200_b0 =3D <0>; + xlnx,otap_delay_mmc_hs200_b0 =3D <0x3>; + xlnx,itap_delay_mmc_hs200_b2 =3D <0>; + xlnx,otap_delay_mmc_hs200_b2 =3D <0x2>; }; smmu: smmu@fd800000 { -- 2.7.4 This email and any attachments are intended for the sole use of the named r= ecipient(s) and contain(s) confidential information that may be proprietary= , privileged or copyrighted under applicable law. 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