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Thu, 07 Jun 2018 05:12:07 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1fQtlq-0001FQ-DU; Thu, 07 Jun 2018 05:12:02 -0700 Received: from xsj-pvapsmtp01 (xsj-smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w57CBx2N001684; Thu, 7 Jun 2018 05:11:59 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1fQtlm-0001Ev-Tb; Thu, 07 Jun 2018 05:11:59 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id 1E4F21214C7; Thu, 7 Jun 2018 17:41:58 +0530 (IST) From: Manish Narani To: , , , , , , , , , , , , CC: Manish Narani Subject: [RFC PATCH 2/3] dt: bindings: Add SD tap value properties details Date: Thu, 7 Jun 2018 17:41:39 +0530 Message-ID: <1528373500-24663-2-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1528373500-24663-1-git-send-email-manish.narani@xilinx.com> References: <1528373500-24663-1-git-send-email-manish.narani@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(346002)(376002)(396003)(39860400002)(39380400002)(2980300002)(438002)(199004)(189003)(2201001)(76176011)(126002)(336012)(106002)(50226002)(90966002)(486006)(6666003)(476003)(103686004)(52956003)(36756003)(446003)(7416002)(47776003)(50466002)(426003)(2906002)(11346002)(48376002)(26005)(2616005)(478600001)(36386004)(316002)(356003)(59450400001)(5660300001)(42186006)(305945005)(4326008)(81156014)(8936002)(51416003)(8676002)(6266002)(81166006)(44832011)(8746002)(5890100001)(186003)(72206003)(63266004)(107886003)(110136005)(106466001)(107986001)(921003)(83996005)(1121003)(2101003)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:BY1PR0201MB0871;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; 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Signed-off-by: Manish Narani --- .../devicetree/bindings/mmc/arasan,sdhci.txt | 26 ++++++++++++++++++= ++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Docum= entation/devicetree/bindings/mmc/arasan,sdhci.txt index 60481bf..0e08877 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -15,6 +15,8 @@ Required Properties: - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY For this device it is strongly suggested to include arasan,soc-ctl-s= yscon. + - "xlnx,zynqmp-8.9a": Xilinx ZynqMP Arasan SDHCI 8.9a PHY + For this device it is strongly suggested to include arasan,soc-ctl-s= yscon. - reg: From mmc bindings: Register location and length. - clocks: From clock bindings: Handles to clock inputs. - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_a= hb" @@ -26,6 +28,30 @@ Required Properties for "arasan,sdhci-5.1": - phys: From PHY bindings: Phandle for the Generic PHY for arasan. - phy-names: MUST be "phy_arasan". +Required Properties for "xlnx,zynqmp-8.9a": + - xlnx,mio_bank: The value will be 0/1/2 depending on MIO bank selection= . + - xlnx,device_id: Unique Id of the device, value will be 0/1. + - xlnx,itap_delay_sd_hsd: Input Tap Delay for SD HS. + - xlnx,itap_delay_sdr25: Input Tap Delay for SDR25. + - xlnx,itap_delay_sdr50: Input Tap Delay for SDR50. + - xlnx,itap_delay_sdr104_b0: Input Tap Delay for SDR104. + - xlnx,itap_delay_sdr104_b2: Input Tap Delay for SDR104. + - xlnx,itap_delay_sd_ddr50: Input Tap Delay for SD DDR50. + - xlnx,itap_delay_mmc_hsd: Input Tap Delay for MMC HS. + - xlnx,itap_delay_mmc_ddr50: Input Tap Delay for MMC DDR50. + - xlnx,itap_delay_mmc_hs200_b0: Input Tap Delay for MMC HS200. + - xlnx,itap_delay_mmc_hs200_b2: Input Tap Delay for MMC HS200. + - xlnx,otap_delay_sd_hsd: Output Tap Delay for SD HS. + - xlnx,otap_delay_sdr25: Output Tap Delay for SDR25. + - xlnx,otap_delay_sdr50: Output Tap Delay for SDR50. + - xlnx,otap_delay_sdr104_b0: Output Tap Delay for SDR104. + - xlnx,otap_delay_sdr104_b2: Output Tap Delay for SDR104. + - xlnx,otap_delay_sd_ddr50: Output Tap Delay for DDR50. + - xlnx,otap_delay_mmc_hsd: Output Tap Delay for MMC HS. + - xlnx,otap_delay_mmc_ddr50: Output Tap Delay for MMC DDR50. + - xlnx,otap_delay_mmc_hs200_b0: Output Tap Delay for MMC HS200. + - xlnx,otap_delay_mmc_hs200_b2: Output Tap Delay for MMC HS200. + Optional Properties: - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon= .txt) used to access core corecfg registers. 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