From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.codeaurora.org by pdx-caf-mail.web.codeaurora.org (Dovecot) with LMTP id y5hHFgDsHVvEIwAAmS7hNA ; Mon, 11 Jun 2018 03:27:08 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CA1A1608B8; Mon, 11 Jun 2018 03:27:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by smtp.codeaurora.org (Postfix) with ESMTP id 0BF0F604D4; Mon, 11 Jun 2018 03:27:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0BF0F604D4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932434AbeFKD1G (ORCPT + 21 others); Sun, 10 Jun 2018 23:27:06 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:18955 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932395AbeFKD1C (ORCPT ); Sun, 10 Jun 2018 23:27:02 -0400 X-UUID: 768d16ae31194e2bb582db154a8e924c-20180611 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1071383607; Mon, 11 Jun 2018 11:26:58 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 11 Jun 2018 11:26:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 11 Jun 2018 11:26:55 +0800 From: Stu Hsieh To: CK Hu , Philipp Zabel CC: David Airlie , Rob Herring , Mark Rutland , Matthias Brugger , , , , , , , Stu Hsieh Subject: [PATCH 13/28] drm/mediatek: add connection from RDMA0 to DSI3 Date: Mon, 11 Jun 2018 11:26:05 +0800 Message-ID: <1528687580-549-14-git-send-email-stu.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> References: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add the connection from RDMA0 to DSI3 Signed-off-by: Stu Hsieh --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index c08aed8dae44..fed1b5704355 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -83,6 +83,7 @@ #define GAMMA_MOUT_EN_RDMA1 0x1 #define RDMA0_MOUT_DPI0 0x2 #define RDMA0_MOUT_DSI2 0x4 +#define RDMA0_MOUT_DSI3 0x5 #define RDMA1_MOUT_DPI0 0x2 #define DPI0_SEL_IN_RDMA1 0x1 #define COLOR1_SEL_IN_OVL1 0x1 @@ -164,6 +165,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { *addr = DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN; value = RDMA0_MOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN; + value = RDMA0_MOUT_DSI3; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; value = RDMA1_MOUT_DPI0; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index fe6fdc021fc7..22f4c72fa785 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -228,7 +228,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL }, - [DDP_COMPONENT_DSI2] = { MTK_DSI, 3, NULL }, + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, -- 2.12.5