From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: ** X-Spam-Status: No, score=2.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,UNWANTED_LANGUAGE_BODY autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by aws-us-west-2-korg-lkml-1.web.codeaurora.org (Postfix) with ESMTP id 36818C433EF for ; Tue, 12 Jun 2018 13:16:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E0041208B0 for ; Tue, 12 Jun 2018 13:16:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E0041208B0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=st.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933817AbeFLNQd (ORCPT ); Tue, 12 Jun 2018 09:16:33 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:1324 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933704AbeFLNQ3 (ORCPT ); Tue, 12 Jun 2018 09:16:29 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w5CDE38q017834; Tue, 12 Jun 2018 15:16:03 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2jjegrr43n-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 12 Jun 2018 15:16:03 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 170F941; Tue, 12 Jun 2018 13:16:01 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id EB7C4A543; Tue, 12 Jun 2018 13:16:00 +0000 (GMT) Received: from SAFEX1HUBCAS21.st.com (10.75.90.44) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 12 Jun 2018 15:16:00 +0200 Received: from lmecxl0923.lme.st.com (10.48.0.237) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 12 Jun 2018 15:16:00 +0200 From: Ludovic Barre To: Ulf Hansson , Rob Herring CC: Maxime Coquelin , Alexandre Torgue , Gerald Baeza , , , , , Ludovic Barre Subject: [PATCH 10/19] mmc: mmci: add variant property to allow remain data Date: Tue, 12 Jun 2018 15:14:31 +0200 Message-ID: <1528809280-31116-11-git-send-email-ludovic.Barre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528809280-31116-1-git-send-email-ludovic.Barre@st.com> References: <1528809280-31116-1-git-send-email-ludovic.Barre@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.48.0.237] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-06-12_01:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ludovic Barre This patch adds a boolean property to read remaining data. Needed to support the STM32 sdmmc variant. MMCIDATACNT register should be read only after the data transfer is complete. When reading after an error event the read data count value may be different from the real number of data bytes transferred. Signed-off-by: Ludovic Barre --- drivers/mmc/host/mmci.c | 17 +++++++++++++++-- drivers/mmc/host/mmci.h | 3 +++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 83c3572..abddad7 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -58,6 +58,7 @@ static struct variant_data variant_arm = { .datalength_bits = 16, .datactrl_blocksz = 11, .datactrl_dpsm_enable = MCI_DPSM_ENABLE, + .datacnt_remain = true, .pwrreg_powerup = MCI_PWR_UP, .f_max = 100000000, .reversed_irq_handling = true, @@ -78,6 +79,7 @@ static struct variant_data variant_arm_extended_fifo = { .datalength_bits = 16, .datactrl_blocksz = 11, .datactrl_dpsm_enable = MCI_DPSM_ENABLE, + .datacnt_remain = true, .pwrreg_powerup = MCI_PWR_UP, .f_max = 100000000, .mmcimask1 = true, @@ -98,6 +100,7 @@ static struct variant_data variant_arm_extended_fifo_hwfc = { .datalength_bits = 16, .datactrl_blocksz = 11, .datactrl_dpsm_enable = MCI_DPSM_ENABLE, + .datacnt_remain = true, .pwrreg_powerup = MCI_PWR_UP, .f_max = 100000000, .mmcimask1 = true, @@ -120,6 +123,7 @@ static struct variant_data variant_u300 = { .datactrl_blocksz = 11, .datactrl_dpsm_enable = MCI_DPSM_ENABLE, .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, + .datacnt_remain = true, .st_sdio = true, .pwrreg_powerup = MCI_PWR_ON, .f_max = 100000000, @@ -146,6 +150,7 @@ static struct variant_data variant_nomadik = { .datactrl_blocksz = 11, .datactrl_dpsm_enable = MCI_DPSM_ENABLE, .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, + .datacnt_remain = true, .st_sdio = true, .st_clkdiv = true, .pwrreg_powerup = MCI_PWR_ON, @@ -175,6 +180,7 @@ static struct variant_data variant_ux500 = { .datactrl_blocksz = 11, .datactrl_dpsm_enable = MCI_DPSM_ENABLE, .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, + .datacnt_remain = true, .st_sdio = true, .st_clkdiv = true, .pwrreg_powerup = MCI_PWR_ON, @@ -209,6 +215,7 @@ static struct variant_data variant_ux500v2 = { .datactrl_blocksz = 11, .datactrl_dpsm_enable = MCI_DPSM_ENABLE, .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, + .datacnt_remain = true, .st_sdio = true, .st_clkdiv = true, .blksz_datactrl16 = true, @@ -244,6 +251,7 @@ static struct variant_data variant_stm32 = { .datactrl_blocksz = 11, .datactrl_dpsm_enable = MCI_DPSM_ENABLE, .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, + .datacnt_remain = true, .st_sdio = true, .st_clkdiv = true, .pwrreg_powerup = MCI_PWR_ON, @@ -270,6 +278,7 @@ static struct variant_data variant_qcom = { .datalength_bits = 24, .datactrl_blocksz = 11, .datactrl_dpsm_enable = MCI_DPSM_ENABLE, + .datacnt_remain = true, .pwrreg_powerup = MCI_PWR_UP, .f_max = 208000000, .explicit_mclk_control = true, @@ -711,8 +720,12 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data, * can be as much as a FIFO-worth of data ahead. This * matters for FIFO overruns only. */ - remain = readl(host->base + MMCIDATACNT); - success = data->blksz * data->blocks - remain; + if (host->variant->datacnt_remain) { + remain = readl(host->base + MMCIDATACNT); + success = data->blksz * data->blocks - remain; + } else { + success = 0; + } dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", status_err, success); diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 5091025..12ee2e6 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -260,6 +260,8 @@ struct mmci_host; * @datactrl_blksz: block size in power of two * @datactrl_dpsm_enable: enable value for DPSM * @datactrl_first: true if data must be setup before send command + * @datacnt_remain: true if you could read datacnt register + * to define remain data * @pwrreg_powerup: power up value for MMCIPOWER register * @f_max: maximum clk frequency supported by the controller. * @signal_direction: input/out direction of bus signals can be indicated @@ -303,6 +305,7 @@ struct variant_data { unsigned int datactrl_blocksz; unsigned int datactrl_dpsm_enable; bool datactrl_first; + bool datacnt_remain; bool st_sdio; bool st_clkdiv; bool blksz_datactrl16; -- 2.7.4