From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01B20C433EF for ; Tue, 19 Jun 2018 08:46:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B49D32083A for ; Tue, 19 Jun 2018 08:46:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B49D32083A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756700AbeFSIqp (ORCPT ); Tue, 19 Jun 2018 04:46:45 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:44459 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1756655AbeFSIql (ORCPT ); Tue, 19 Jun 2018 04:46:41 -0400 X-UUID: 8c13ba7c52da4a5292af8bcd544698a0-20180619 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 531602735; Tue, 19 Jun 2018 16:46:37 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 19 Jun 2018 16:46:35 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 19 Jun 2018 16:46:35 +0800 Message-ID: <1529397995.26480.19.camel@mtksdaap41> Subject: Re: [PATCH v6 23/29] drm/mediatek: add connection from RDMA2 to DSI2 From: CK Hu To: Stu Hsieh CC: Philipp Zabel , David Airlie , Rob Herring , Mark Rutland , Matthias Brugger , , , , , , Date: Tue, 19 Jun 2018 16:46:35 +0800 In-Reply-To: <1529393670-26862-24-git-send-email-stu.hsieh@mediatek.com> References: <1529393670-26862-1-git-send-email-stu.hsieh@mediatek.com> <1529393670-26862-24-git-send-email-stu.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2018-06-19 at 15:34 +0800, Stu Hsieh wrote: > This patch add the connection from RDMA2 to DSI2 > Reviewed-by: CK Hu > Signed-off-by: Stu Hsieh > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index db78fad785e3..e5db1ab51c9b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -95,6 +95,7 @@ > #define RDMA2_SOUT_DPI0 0x2 > #define RDMA2_SOUT_DPI1 0x3 > #define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > #define DPI0_SEL_IN_RDMA1 0x1 > #define DPI0_SEL_IN_RDMA2 0x3 > #define DPI1_SEL_IN_RDMA1 (0x1 << 8) > @@ -102,6 +103,7 @@ > #define DSI1_SEL_IN_RDMA1 0x1 > #define DSI1_SEL_IN_RDMA2 0x4 > #define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > #define DSI3_SEL_IN_RDMA1 (0x1 << 16) > #define COLOR1_SEL_IN_OVL1 0x1 > > @@ -209,6 +211,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > } else { > value = 0; > } > @@ -249,6 +254,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > value = COLOR1_SEL_IN_OVL1;