From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0474C43142 for ; Fri, 22 Jun 2018 16:09:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8F6BD24584 for ; Fri, 22 Jun 2018 16:09:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nifty.com header.i=@nifty.com header.b="AQczH5FQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8F6BD24584 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934188AbeFVQIh (ORCPT ); Fri, 22 Jun 2018 12:08:37 -0400 Received: from conuserg-12.nifty.com ([210.131.2.79]:30612 "EHLO conuserg-12.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934044AbeFVQIQ (ORCPT ); Fri, 22 Jun 2018 12:08:16 -0400 Received: from grover.sesame (FL1-125-199-20-195.osk.mesh.ad.jp [125.199.20.195]) (authenticated) by conuserg-12.nifty.com with ESMTP id w5MG6m5d022587; Sat, 23 Jun 2018 01:06:51 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com w5MG6m5d022587 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1529683612; bh=bDbRzl/Y7hMBUMFMuM7lmIwqpkfuICtect6xSmzsPQQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AQczH5FQ4yZ551ASNksC9ntV1Bq1IQh5c+idQ6JtH7GaylyRdYblxD/DSmUgicjUS xBkh3tjVhpP/M3YRkNOqeRzq6TyI6+TKMcKO0ntlDW4B1CrTWIqGUJdyppPU4+/mmh a+hOj19SoPk8dLCo9RP0CRQKqMT6XI3BjkvaMnFOeZPGc0jweYG8QAtPXSUufZDFoh fDYrvRF2R/JfBD3sHd5oUfMzRBfwxuHgEiUmw9B/eeoeWaWraIPGCaqQS3wbgR0h/B A/IBUGSs04uD/bK0zhWAmMQPesy9L+XfEZ/XuoWQBxWTpnrNI3df5/zIIEzoPy3GJR +80n0625x/4Vw== X-Nifty-SrcIP: [125.199.20.195] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Boris Brezillon Cc: Rob Herring , Miquel Raynal , Richard Weinberger , Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Marek Vasut , Brian Norris , David Woodhouse , Mark Rutland Subject: [PATCH v4 3/5] dt-binding: mtd: denali_dt: document clock property Date: Sat, 23 Jun 2018 01:06:36 +0900 Message-Id: <1529683598-25783-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529683598-25783-1-git-send-email-yamada.masahiro@socionext.com> References: <1529683598-25783-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit 30f9f2fb7ba0 ("mtd: denali: add a DT driver") supported the clock enablement, but did not document it in the DT binding. In addition to the existing clock, this commit adds more clocks based on the IP specification. According to the Denali User's Guide, this IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run The driver should accept the current single clock for the backward compatibility, but the DT binding should represent the real hardware, and future platforms must follow this. Signed-off-by: Masahiro Yamada --- Changes in v4: - split into a separate patch Documentation/devicetree/bindings/mtd/denali-nand.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt index 0ee8edb..f33da87 100644 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt @@ -8,6 +8,9 @@ Required properties: - reg : should contain registers location and length for data and reg. - reg-names: Should contain the reg names "nand_data" and "denali_reg" - interrupts : The interrupt number. + - clocks: should contain phandle of the controller core clock, the bus + interface clock, and the ECC circuit clock. + - clock-names: should contain "nand", "nand_x", "ecc" Optional properties: - nand-ecc-step-size: see nand.txt for details. If present, the value must be @@ -31,5 +34,7 @@ nand: nand@ff900000 { compatible = "altr,socfpga-denali-nand"; reg = <0xff900000 0x20>, <0xffb80000 0x1000>; reg-names = "nand_data", "denali_reg"; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; interrupts = <0 144 4>; }; -- 2.7.4