From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2A0FC5CFE7 for ; Wed, 11 Jul 2018 14:01:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7541D208EC for ; Wed, 11 Jul 2018 14:01:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7541D208EC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388326AbeGKOGU (ORCPT ); Wed, 11 Jul 2018 10:06:20 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18613 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387708AbeGKOGU (ORCPT ); Wed, 11 Jul 2018 10:06:20 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Wed, 11 Jul 2018 07:01:05 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 11 Jul 2018 07:01:46 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 11 Jul 2018 07:01:46 -0700 Received: from dhcp-10-21-25-168.Nvidia.com (10.21.25.201) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 11 Jul 2018 14:01:47 +0000 From: Aapo Vienamo To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Mikko Perttunen CC: Aapo Vienamo , , , Subject: [PATCH v2 0/7] Tegra PMC pinctrl pad configuration Date: Wed, 11 Jul 2018 17:01:26 +0300 Message-ID: <1531317693-3520-1-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.21.25.201] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To HQMAIL101.nvidia.com (172.20.187.10) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, The Tegra Power Management Controller (PMC) can set pad power states and voltage configuration. This series implements pinctrl interfaces for configuring said pad properties. Changelog v2: - Add Tegra186 AO_HV pad - Make the IO pad tables narrower - Add parens to TEGRA_IO_PAD() and TEGRA_IO_PIN_DESC() - Fix a typo in the dt-bindings docs - Remove old pmc pad voltage configuration APIs - Check return value of tegra_io_pad_find() in tegra_io_pad_pinconf_get()/_set() Aapo Vienamo (7): soc/tegra: pmc: Fix pad voltage configuration for Tegra186 soc/tegra: pmc: Factor out DPD register bit calculation soc/tegra: pmc: Implement tegra_io_pad_is_powered() soc/tegra: pmc: Use X macro to generate IO pad tables dt-bindings: Add Tegra PMC pad configuration bindings soc/tegra: pmc: Remove public pad voltage APIs soc/tegra: pmc: Implement pad configuration via pinctrl .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 84 ++++ .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 95 ++++ drivers/soc/tegra/pmc.c | 513 +++++++++++++++------ include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | 18 + include/soc/tegra/pmc.h | 15 +- 5 files changed, 583 insertions(+), 142 deletions(-) create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h -- 2.7.4