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Wed, 18 Jul 2018 13:39:47 +0000 From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, mturquette@baylibre.com, shawnguo@kernel.org, Anson.Huang@nxp.com, ping.bai@nxp.com, linux-imx@nxp.com, Dong Aisheng Subject: [PATCH V4 0/9] clk: add imx7ulp clk support Date: Wed, 18 Jul 2018 21:36:54 +0800 Message-Id: <1531921023-18497-1-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: HK0PR03CA0090.apcprd03.prod.outlook.com (2603:1096:203:72::30) To DB7PR04MB4219.eurprd04.prod.outlook.com (2603:10a6:5:27::16) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e1da4e02-7e9d-41f9-7ec5-08d5ecb3f012 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989117)(5600053)(711020)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(48565401081)(2017052603328)(7153060)(7193020);SRVR:DB7PR04MB4219; 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[PATCH RESEND V3 0/9] clk: add imx7ulp clk support https://lkml.org/lkml/2018/3/16/310 This patch series intends to add imx7ulp clk support. i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared between two domains, such as the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC clock (FIRCLK), clock sources and clock management are separated and contained within each domain. M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. Note: this series only adds A7 clock domain support as M4 clock domain will be handled by M4 seperately. Change Log: v3->v4: * rebased to latest kernel * make scg and pcc separate nodes according to Rob's suggestion v2->v3: * Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy Others no changes. v1->v2: * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers * use clk_hw apis to register clocks * use of_clk_add_hw_provider * split the clocks register process into two parts: early part for possible timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for the left normal peripheral clocks registered by a platform driver. Dong Aisheng (9): clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add pllv4 support clk: imx: add pfdv2 support clk: imx: add composite clk support dt-bindings: clock: add imx7ulp clock binding doc clk: imx: make mux parent strings const clk: imx: implement new clk_hw based APIs clk: imx: add imx7ulp clk driver .../devicetree/bindings/clock/imx7ulp-clock.txt | 87 +++++++++ drivers/clk/clk-divider.c | 152 +++++++++++++++ drivers/clk/clk-fractional-divider.c | 10 + drivers/clk/imx/Makefile | 6 +- drivers/clk/imx/clk-busy.c | 2 +- drivers/clk/imx/clk-composite.c | 85 +++++++++ drivers/clk/imx/clk-fixup-mux.c | 2 +- drivers/clk/imx/clk-imx7ulp.c | 209 +++++++++++++++++++++ drivers/clk/imx/clk-pfdv2.c | 201 ++++++++++++++++++++ drivers/clk/imx/clk-pllv4.c | 182 ++++++++++++++++++ drivers/clk/imx/clk.c | 22 +++ drivers/clk/imx/clk.h | 92 ++++++++- include/dt-bindings/clock/imx7ulp-clock.h | 109 +++++++++++ include/linux/clk-provider.h | 17 ++ 14 files changed, 1166 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt create mode 100644 drivers/clk/imx/clk-composite.c create mode 100644 drivers/clk/imx/clk-imx7ulp.c create mode 100644 drivers/clk/imx/clk-pfdv2.c create mode 100644 drivers/clk/imx/clk-pllv4.c create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h -- 2.7.4