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Thu, 19 Jul 2018 03:06:02 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1fg5or-0003wa-Gq; Thu, 19 Jul 2018 03:05:57 -0700 Received: from xsj-pvapsmtp01 (mailhub.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w6JA5q8F015619; Thu, 19 Jul 2018 03:05:52 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1fg5ol-0003vm-Uf; Thu, 19 Jul 2018 03:05:52 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id 16B3C1214FE; Thu, 19 Jul 2018 15:35:51 +0530 (IST) From: Manish Narani To: , , , , , CC: , , Manish Narani Subject: [PATCH 2/4] dt: bindings: Document ZynqMP DDRC in Synopsys documentation Date: Thu, 19 Jul 2018 15:35:45 +0530 Message-ID: <1531994747-15196-3-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1531994747-15196-1-git-send-email-manish.narani@xilinx.com> References: <1531994747-15196-1-git-send-email-manish.narani@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(346002)(376002)(136003)(39860400002)(396003)(2980300002)(438002)(189003)(199004)(63266004)(81166006)(81156014)(103686004)(50466002)(2616005)(36386004)(48376002)(72206003)(44832011)(478600001)(486006)(6266002)(126002)(4326008)(476003)(8676002)(426003)(106466001)(2906002)(11346002)(47776003)(90966002)(446003)(356003)(76176011)(8936002)(107886003)(51416003)(16586007)(110136005)(316002)(42186006)(54906003)(106002)(5660300001)(186003)(26005)(6666003)(50226002)(36756003)(305945005)(2201001)(52956003)(336012)(107986001)(2101003);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1PR0201MB1915;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; 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Signed-off-by: Manish Narani --- .../bindings/memory-controllers/synopsys.txt | 25 ++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt index a43d26d..5d20b76 100644 --- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt @@ -1,15 +1,32 @@ Binding for Synopsys IntelliDDR Multi Protocol Memory Controller -This controller has an optional ECC support in half-bus width (16-bit) -configuration. The ECC controller corrects one bit error and detects +Synopsys EDAC driver, it does reports the DDR ECC single bit errors +that are corrected and double bit ecc errors that are detected by the DDR +ECC controller. + +The Zynq DDR ECC controller has an optional ECC support in half-bus width +(16-bit) configuration. The ECC controller corrects one bit error and detects two bit errors. Required properties: - - compatible: Should be 'xlnx,zynq-ddrc-a05' - - reg: Base address and size of the controllers memory area + - compatible: One of: + - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller + - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller + - reg: Should contain DDR controller registers location and length. + +Required properties for "xlnx,zynqmp-ddrc-2.40a": + - interrupt-parent: Should be core interrupt controller. + - interrupts: Property with a value describing the interrupt number. Example: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; + + mc: memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0x0 0xfd070000 0x0 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; -- 2.1.1