From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D25D3ECDE5F for ; Mon, 23 Jul 2018 10:09:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8C9C020854 for ; Mon, 23 Jul 2018 10:09:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linaro.org header.i=@linaro.org header.b="aafJerS+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8C9C020854 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388406AbeGWLJy (ORCPT ); Mon, 23 Jul 2018 07:09:54 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:35609 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388246AbeGWLJy (ORCPT ); Mon, 23 Jul 2018 07:09:54 -0400 Received: by mail-pf1-f196.google.com with SMTP id q7-v6so12376pff.2 for ; Mon, 23 Jul 2018 03:09:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Vwl51bqmcDS8wp+lU1pZalSc7Z3bokmXBYlYRayzf+k=; b=aafJerS+Wy98Bqo54iiJlRRZ4XSAOzDYKbZmcV904pGjNkYIXGPlN5ERHKshAVYb+P rBSye5CXK+IrnLSQNwvnPqy/SrWY9XFvGR96twNi3hVDMB92dIXj8Lp0UzcPOd9Du1z3 ugMc20CHPyUB9xiuV/yTi2YA0W/pcQgkmzycE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Vwl51bqmcDS8wp+lU1pZalSc7Z3bokmXBYlYRayzf+k=; b=tmXyUpJQyu5Zk/a67DO6XBv0qtMM/33pISo4OoMzfbhwfzgXC1h/62Gqpq2nLqwTNU VJMxdIJyQQKg9zKwKgaAlUY1baQpx0IZzXkRGwZGSau1dVLxd9Pil8fdku1CtjK6+Dzh bk/Pog8u+QIUz8zOw1DUCVyIQy3XevhnA6AKiiCixEkF3VrJr5byc7jcpv5rn0hY/Jsd 87xKiwZmnyn1XMhHgHyIRdJCqc1P0CZwI0RzCTjAUfzhVR6ejfcopr3oD05qvRtHp0Z7 D3K9WyBknrqOY/i5efSDONScL/Cc+aIiknvM5wbBHKdmSPHxRZFmfI67q7lSFOg1hZPV jVXg== X-Gm-Message-State: AOUpUlErjOen+cimKRYXfPkhds7OwEu52DgCSgtiicwlXQQVYPBX0US5 hcALH1hhohc2KFE9rcL/hT8NBA== X-Google-Smtp-Source: AAOMgpeGj6vysc0vE8BADSpgdQXoBJDDXsSN8FHAVGSp9NhbObNDyUuDKkGJG40D5rkwWeNeeO/7zQ== X-Received: by 2002:a65:6203:: with SMTP id d3-v6mr11649605pgv.420.1532340567315; Mon, 23 Jul 2018 03:09:27 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id e82-v6sm13470698pfk.87.2018.07.23.03.09.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 03:09:26 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , zhang.lyra@gmail.com Subject: [PATCH V4 4/7] mmc: sdhci: add 32-bit block count support for v4 mode Date: Mon, 23 Jul 2018 18:08:25 +0800 Message-Id: <1532340508-8749-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532340508-8749-1-git-send-email-zhang.chunyan@linaro.org> References: <1532340508-8749-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 15 ++++++++++++++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ce71afa..5acea3d 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -956,6 +956,7 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { + u32 reg; struct mmc_data *data = cmd->data; host->data_timeout = 0; @@ -1070,7 +1071,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 16-bit Block Count + * register need to be set to zero, 32-bit Block Count register would + * be selected. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 23318ff..81aae07 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) -- 2.7.4