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Tue, 24 Jul 2018 06:04:11 +0000 From: Bharat Bhushan To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Cc: Bharat Bhushan Subject: [PATCH] powerpc/e200: Skip tlb1 entries used for kernel mapping Date: Tue, 24 Jul 2018 11:29:45 +0530 Message-Id: <1532411985-17725-1-git-send-email-Bharat.Bhushan@nxp.com> X-Mailer: git-send-email 1.9.3 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR0101CA0057.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:19::19) To HE1PR0401MB2556.eurprd04.prod.outlook.com (2603:10a6:3:84::10) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ad2dc4c3-24d1-42cf-2e4d-08d5f12b4764 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989117)(5600073)(711020)(4618075)(4534165)(7168020)(4627221)(201703031133081)(201702281549075)(8990107)(2017052603328)(7153060)(7193020);SRVR:HE1PR0401MB2556; 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So TLB1 are used for mapping kernel and user-space both. TLB miss handler for E200 does not consider skipping TLBs used for kernel mapping. This patch ensures that we skip tlb1 entries used for kernel mapping (tlbcam_index). Signed-off-by: Bharat Bhushan --- arch/powerpc/kernel/head_fsl_booke.S | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index bf4c602..951fb96 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -801,12 +801,28 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) /* Round robin TLB1 entries assignment */ mfspr r12, SPRN_MAS0 + /* Get first free tlbcam entry */ + lis r11, tlbcam_index@ha + lwz r11, tlbcam_index@l(r11) + + /* Extract MAS0(NV) */ + andi. r13, r12, 0xfff + cmpw 0, r13, r11 + blt 0, 5f + b 6f +5: + /* When NV is less than first free tlbcam entry, use first free + * tlbcam entry for ESEL and set NV */ + rlwimi r12, r11, 16, 4, 15 + addi r11, r11, 1 + rlwimi r12, r11, 0, 20, 31 + b 7f +6: /* Extract TLB1CFG(NENTRY) */ mfspr r11, SPRN_TLB1CFG andi. r11, r11, 0xfff - /* Extract MAS0(NV) */ - andi. r13, r12, 0xfff + /* Set MAS0(NV) for next TLB miss exception */ addi r13, r13, 1 cmpw 0, r13, r11 addi r12, r12, 1 -- 1.9.3