From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E915C28CF6 for ; Thu, 26 Jul 2018 12:27:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3D25920894 for ; Thu, 26 Jul 2018 12:27:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3D25920894 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731534AbeGZNnw (ORCPT ); Thu, 26 Jul 2018 09:43:52 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:16988 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730175AbeGZNnv (ORCPT ); Thu, 26 Jul 2018 09:43:51 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Thu, 26 Jul 2018 05:27:15 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 26 Jul 2018 05:27:14 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 26 Jul 2018 05:27:14 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 26 Jul 2018 12:27:14 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 26 Jul 2018 12:27:13 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Thu, 26 Jul 2018 12:27:13 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 26 Jul 2018 05:27:13 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , "Adrian Hunter" , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH v2 04/10] mmc: tegra: Disable card clock during pad calibration Date: Thu, 26 Jul 2018 15:26:50 +0300 Message-ID: <1532608016-14319-5-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532608016-14319-1-git-send-email-avienamo@nvidia.com> References: <1532608016-14319-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Disable the card clock during automatic pad drive strength calibration and re-enable it afterwards. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 363490e..79ecdd0 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -259,11 +259,35 @@ static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) udelay(1); } +static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) +{ + bool orig_enabled; + u32 reg; + + reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + orig_enabled = !!(reg & SDHCI_CLOCK_CARD_EN); + + if (orig_enabled == enable) + return orig_enabled; + + if (enable) + reg |= SDHCI_CLOCK_CARD_EN; + else + reg &= ~SDHCI_CLOCK_CARD_EN; + + sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); + + return orig_enabled; +} + static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) { + bool card_clk_enabled; u32 reg; int ret; + card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); + tegra_sdhci_configure_cal_pad(host, true); reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); @@ -277,6 +301,8 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) tegra_sdhci_configure_cal_pad(host, false); + tegra_sdhci_configure_card_clk(host, card_clk_enabled); + if (ret) dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); } -- 2.7.4