From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FA11C04EBF for ; Tue, 4 Dec 2018 01:37:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F1C9B2146D for ; Tue, 4 Dec 2018 01:37:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="loPEhGc9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F1C9B2146D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726183AbeLDBhN (ORCPT ); Mon, 3 Dec 2018 20:37:13 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17659 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726031AbeLDBhJ (ORCPT ); Mon, 3 Dec 2018 20:37:09 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 03 Dec 2018 17:37:07 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 03 Dec 2018 17:37:08 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 03 Dec 2018 17:37:08 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 01:37:07 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 01:37:07 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 03 Dec 2018 17:37:07 -0800 From: Krishna Reddy To: , , CC: , , , , , , , , , , , , , , Krishna Reddy Subject: [PATCH v3 6/6] arm64: tegra: Add SMMU nodes to Tegra194 device tree Date: Mon, 3 Dec 2018 17:36:54 -0800 Message-ID: <1543887414-18209-7-git-send-email-vdumpa@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1543887414-18209-1-git-send-email-vdumpa@nvidia.com> References: <1543887414-18209-1-git-send-email-vdumpa@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543887427; bh=7rVLqrMpNN7Me2iDOh5vNXLMCVcrzNs8j3X4P53Vhp8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=loPEhGc9H9xJb+Pp5i1RiEpA5i1+rOE5rm5lCUSBe47SQwE3bXxahlY++h4x7f+1h uaDnub6oMHHlcZ8NhB7WJslKBetDfw2l+oG9n/opay2unm12mFW+bC72GfcOaCcEuw Gs1n/b6hUk6oBQn6g+AlioWkjCueOYUo4q09kQd1rtpxDAdKSEw2TMy/Empsmbrqdr sp2fkL8pP3SgXRsQA1oQ5lGzYXUz8N0N1pmVlW7uMO9+sZGA3W6TriNnlE2z8HIr90 6DCuTElyX1u7aBn9y3RjDKMZztiOMUofqD/78CwlyI4U00NhAr/FZk1SeZraeLOYvC JwrO+kHsZGWEg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add SMMU nodes and dma-ranges to Tegra194 device tree. Tegra194 has three ARM SMMU Instances. Two of them are used together to access IOVA interleaved. The third one is used as regular ARM SMMU. Signed-off-by: Krishna Reddy --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 148 +++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f274562..9a3e08c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -12,6 +12,7 @@ interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; + dma-ranges = <0x0 0x0 0x0 0x0 0x8 0x0>; /* control backbone */ cbb { @@ -957,4 +958,151 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&gic>; }; + + dualsmmu: iommu@12000000 { + compatible = "tegra194,arm,mmu-500"; + reg = <0 0x12000000 0 0x800000>, + <0 0x11000000 0 0x800000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <1>; + #iommu-cells = <1>; + }; + + smmu: iommu@10000000 { + compatible = "arm,mmu-500"; + reg = <0 0x10000000 0 0x800000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <1>; + #iommu-cells = <1>; + }; }; -- 2.1.4