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received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: agPynI1t6s2cUd+BVCye79OVqYMiozce8AH+58FfiUEO231lyh/nigAveUiNJDBvE5BQXZBuy3X/EXJkOmvsIN2vMTPjRGeT9dW3aU9Y44SsTq0F9GgBqXeiOuwig1nmGTZsBb6wDeynkpnEKs9LTcR4oLGWWtjc/l/4EHklqnI+/bxMK+EzJr0iCeSsZXPWf8YjCVzCZK/YDDP5jZoVdAJjsimgY3exye2er+81+L5J4xlLZ8JsP98hvS09APe/lio19WCTJaAYzpOMzTmA95PmykQ3ZLD2cIZJBCufEm19VVlrPVMbFQ6fDNMnc0Pi spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 12ef0c84-5501-4b81-6cdc-08d664287327 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Dec 2018 14:03:41.6910 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR11MB0646 X-OriginatorOrg: microchip.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Claudiu Beznea Add support for PWM push-pull mode. This is only supported by SAMA5D2 SoCs. Signed-off-by: Claudiu Beznea --- drivers/pwm/pwm-atmel.c | 40 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index b72cacd5dca3..650d475a4c34 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -33,8 +33,11 @@ =20 #define PWM_CMR 0x0 /* Bit field in CMR */ -#define PWM_CMR_CPOL (1 << 9) -#define PWM_CMR_UPD_CDTY (1 << 10) +#define PWM_CMR_CPOL BIT(9) +#define PWM_CMR_UPD_CDTY BIT(10) +#define PWM_CMR_DTHI BIT(17) +#define PWM_CMR_DTLI BIT(18) +#define PWM_CMR_PPM BIT(19) #define PWM_CMR_CPRE_MSK 0xF =20 /* The following registers for PWM v1 */ @@ -219,16 +222,19 @@ static int atmel_pwm_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, { struct atmel_pwm_chip *atmel_pwm =3D to_atmel_pwm_chip(chip); struct pwm_state cstate; + struct pwm_caps caps; unsigned long cprd, cdty; u32 pres, val; int ret; =20 pwm_get_state(pwm, &cstate); + pwm_get_caps(pwm, &caps); =20 if (state->enabled) { if (cstate.enabled && cstate.polarity =3D=3D state->polarity && - cstate.period =3D=3D state->period) { + cstate.period =3D=3D state->period && + cstate.modebit =3D=3D state->modebit) { cprd =3D atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, atmel_pwm->data->regs.period); atmel_pwm_calculate_cdty(state, cprd, &cdty); @@ -263,6 +269,18 @@ static int atmel_pwm_apply(struct pwm_chip *chip, stru= ct pwm_device *pwm, val &=3D ~PWM_CMR_CPOL; else val |=3D PWM_CMR_CPOL; + + /* PWM mode. */ + if (caps.modes_msk & PWM_MODE_BIT(PUSH_PULL)) { + if (state->modebit =3D=3D PWM_MODE_BIT(PUSH_PULL)) { + val |=3D PWM_CMR_PPM | PWM_CMR_DTLI; + val &=3D ~PWM_CMR_DTHI; + } else { + val &=3D ~(PWM_CMR_PPM | PWM_CMR_DTLI | + PWM_CMR_DTHI); + } + } + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty); mutex_lock(&atmel_pwm->isr_lock); @@ -319,6 +337,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = =3D { }, }; =20 +static const struct atmel_pwm_data atmel_pwm_data_v3 =3D { + .regs =3D { + .period =3D PWMV2_CPRD, + .period_upd =3D PWMV2_CPRDUPD, + .duty =3D PWMV2_CDTY, + .duty_upd =3D PWMV2_CDTYUPD, + }, + .caps =3D { + .modes_msk =3D PWM_MODE_BIT(NORMAL) | + PWM_MODE_BIT(COMPLEMENTARY) | + PWM_MODE_BIT(PUSH_PULL), + }, +}; + static const struct platform_device_id atmel_pwm_devtypes[] =3D { { .name =3D "at91sam9rl-pwm", @@ -341,7 +373,7 @@ static const struct of_device_id atmel_pwm_dt_ids[] =3D= { .data =3D &atmel_pwm_data_v2, }, { .compatible =3D "atmel,sama5d2-pwm", - .data =3D &atmel_pwm_data_v2, + .data =3D &atmel_pwm_data_v3, }, { /* sentinel */ }, --=20 2.7.4