From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79F78C43387 for ; Wed, 26 Dec 2018 05:27:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 542F521720 for ; Wed, 26 Dec 2018 05:27:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725978AbeLZF1S (ORCPT ); Wed, 26 Dec 2018 00:27:18 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:47817 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725891AbeLZF1S (ORCPT ); Wed, 26 Dec 2018 00:27:18 -0500 X-UUID: f440a9f4df25492cb767a0d773e77b75-20181226 X-UUID: f440a9f4df25492cb767a0d773e77b75-20181226 Received: from mtkcas32.mediatek.inc [(172.27.4.250)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1929029755; Wed, 26 Dec 2018 13:27:12 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 26 Dec 2018 13:27:10 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 26 Dec 2018 13:27:10 +0800 Message-ID: <1545802030.14496.25.camel@mtksdaap41> Subject: Re: [PATCH 05/18] drm/mediatek: add ddp component CCORR From: CK Hu To: Yongqiang Niu CC: Philipp Zabel , David Airlie , Rob Herring , Mark Rutland , Matthias Brugger , , , , , Date: Wed, 26 Dec 2018 13:27:10 +0800 In-Reply-To: <1545638931-24938-6-git-send-email-yongqiang.niu@mediatek.com> References: <1545638931-24938-1-git-send-email-yongqiang.niu@mediatek.com> <1545638931-24938-6-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Mon, 2018-12-24 at 16:08 +0800, Yongqiang Niu wrote: > This patch add ddp component CCORR Reviewed-by: CK Hu > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32 +++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++ > 2 files changed, 34 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 54ca794..310c0b9 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -41,6 +41,12 @@ > #define DISP_AAL_EN 0x0000 > #define DISP_AAL_SIZE 0x0030 > > +#define DISP_CCORR_EN 0x0000 > +#define CCORR_EN BIT(0) > +#define DISP_CCORR_CFG 0x0020 > +#define CCORR_RELAY_MODE BIT(0) > +#define DISP_CCORR_SIZE 0x0030 > + > #define DISP_GAMMA_EN 0x0000 > #define DISP_GAMMA_CFG 0x0020 > #define DISP_GAMMA_SIZE 0x0030 > @@ -131,6 +137,24 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp) > writel_relaxed(0x0, comp->regs + DISP_AAL_EN); > } > > +static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc) > +{ > + writel(h << 16 | w, comp->regs + DISP_CCORR_SIZE); > + writel(CCORR_RELAY_MODE, comp->regs + DISP_CCORR_CFG); > +} > + > +static void mtk_ccorr_start(struct mtk_ddp_comp *comp) > +{ > + writel(CCORR_EN, comp->regs + DISP_CCORR_EN); > +} > + > +static void mtk_ccorr_stop(struct mtk_ddp_comp *comp) > +{ > + writel_relaxed(0x0, comp->regs + DISP_CCORR_EN); > +} > + > static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc) > @@ -179,6 +203,12 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, > .stop = mtk_aal_stop, > }; > > +static const struct mtk_ddp_comp_funcs ddp_ccorr = { > + .config = mtk_ccorr_config, > + .start = mtk_ccorr_start, > + .stop = mtk_ccorr_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_gamma = { > .gamma_set = mtk_gamma_set, > .config = mtk_gamma_config, > @@ -200,6 +230,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, > [MTK_DISP_RDMA] = "rdma", > [MTK_DISP_WDMA] = "wdma", > [MTK_DISP_COLOR] = "color", > + [MTK_DISP_CCORR] = "ccorr", > [MTK_DISP_AAL] = "aal", > [MTK_DISP_GAMMA] = "gamma", > [MTK_DISP_UFOE] = "ufoe", > @@ -221,6 +252,7 @@ struct mtk_ddp_comp_match { > [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, > [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index 8399229..87ef290 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -28,6 +28,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_RDMA, > MTK_DISP_WDMA, > MTK_DISP_COLOR, > + MTK_DISP_CCORR, > MTK_DISP_AAL, > MTK_DISP_GAMMA, > MTK_DISP_UFOE, > @@ -44,6 +45,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_AAL0, > DDP_COMPONENT_AAL1, > DDP_COMPONENT_BLS, > + DDP_COMPONENT_CCORR, > DDP_COMPONENT_COLOR0, > DDP_COMPONENT_COLOR1, > DDP_COMPONENT_DPI0,