From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56C23C43387 for ; Tue, 1 Jan 2019 03:58:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1D13C2075D for ; Tue, 1 Jan 2019 03:58:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728315AbfAAD6a (ORCPT ); Mon, 31 Dec 2018 22:58:30 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:39998 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728271AbfAAD63 (ORCPT ); Mon, 31 Dec 2018 22:58:29 -0500 X-UUID: f4e94fcf1a0d423b94277e4dc815d045-20190101 X-UUID: f4e94fcf1a0d423b94277e4dc815d045-20190101 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1382668491; Tue, 01 Jan 2019 11:58:23 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 1 Jan 2019 11:58:22 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 1 Jan 2019 11:58:21 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Robin Murphy , Rob Herring CC: Tomasz Figa , Will Deacon , , , , , , , , , , , Nicolas Boichat Subject: [PATCH v5 10/20] iommu/mediatek: Move reset_axi into plat_data Date: Tue, 1 Jan 2019 11:55:42 +0800 Message-ID: <1546314952-15990-11-git-send-email-yong.wu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1546314952-15990-1-git-send-email-yong.wu@mediatek.com> References: <1546314952-15990-1-git-send-email-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In mt8173 and mt8183, 0x48 is REG_MMU_STANDARD_AXI_MODE while it is extended to REG_MMU_CTRL which contains _STANDARD_AXI_MODE in the other SoCs. I move this property to plat_data since both mt8173 and mt8183 use this property. It is a preparing patch for mt8183. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 4 ++-- drivers/iommu/mtk_iommu.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 35a1263..8d8ab21 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -558,8 +558,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) } writel_relaxed(0, data->base + REG_MMU_DCM_DIS); - /* It's MISC control register whose default value is ok except mt8173.*/ - if (data->plat_data->m4u_plat == M4U_MT8173) + if (data->plat_data->reset_axi) writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, @@ -749,6 +748,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) .m4u_plat = M4U_MT8173, .has_4gb_mode = true, .has_bclk = true, + .reset_axi = true, .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ }; diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index eec19a6..b46aeaa 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -47,7 +47,7 @@ struct mtk_iommu_plat_data { /* HW will use the EMI clock if there isn't the "bclk". */ bool has_bclk; - + bool reset_axi; unsigned char larbid_remap[MTK_LARB_NR_MAX]; }; -- 1.9.1