From: Mikael Pettersson <mikpe@csd.uu.se>
To: Martin Wilck <Martin.Wilck@fujitsu-siemens.com>
Cc: Linux Kernel mailing list <linux-kernel@vger.kernel.org>
Subject: Re: PROBLEM: Timer interrupt lockup on HT machine
Date: Thu, 28 Feb 2002 18:21:50 +0100 [thread overview]
Message-ID: <15486.26414.396199.94258@harpo.it.uu.se> (raw)
In-Reply-To: <Pine.LNX.4.33.0202281339290.24779-100000@biker.pdb.fsc.net>
In-Reply-To: <Pine.LNX.4.33.0202281339290.24779-100000@biker.pdb.fsc.net>
Martin Wilck writes:
> Another observation is that on the HT machines (whether or not the
> above problem occurs) almost all interrupts seem to be handled by CPU 0.
>
> CPU 1 gets a few, but in a ratio of about 1:10000 wrt CPU 0.
> CPU 2 and 3 do not see any interrupts at all.
>
> Has anybody heard of these problems yet, and are workarounds available?
I've heard about that IRQ imbalance on MP P4 Xeons from a person at Dell.
My understanding of it is that it's a consequence of the local APIC
priorization changes Intel did in the P4 xAPIC design. (Study Intel's IA32
Vol 3 manual in detail and you'll see them.) Supposedly Ingo Molnar is
working on a solution.
/Mikael
next prev parent reply other threads:[~2002-02-28 17:27 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-02-28 12:48 Martin Wilck
2002-02-28 17:21 ` Mikael Pettersson [this message]
2002-02-28 20:28 ` Martin Wilck
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