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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0203df92-921d-4c06-16d7-08d686b3ab43 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Jan 2019 13:05:51.7579 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4211 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Not all 64 interrupts may be used in one group. e.g. most irqsteer in imx8qxp and imx8qm subsystems supports only 32 interrupts. As the IP integration parameters are Channel number and interrupts number, let's use fsl,num-irqs to represents how many interrupts supported by this irqsteer channel. Cc: Marc Zyngier Cc: Rob Herring Cc: Lucas Stach Cc: Shawn Guo Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng --- ChangeLog: v1->v2: * change property name fsl,irqs-per-chan to fsl,num-irqs. --- .../devicetree/bindings/interrupt-controller/fsl,irqsteer.txt | 6 ++= +--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irq= steer.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqs= teer.txt index 45790ce..6d0a41b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.t= xt +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.t= xt @@ -16,8 +16,8 @@ Required properties: - #interrupt-cells: Specifies the number of cells needed to encode an interrupt source. The value must be 1. - fsl,channel: The output channel that all input IRQs should be steered in= to. -- fsl,irq-groups: Number of IRQ groups managed by this controller instance= . - Each group manages 64 input interrupts. +- fsl,num-irqs: Number of input interrupts of this channel. + Should be multiple of 32 input interrupts and up to 512 interrupts. =20 Example: =20 @@ -28,7 +28,7 @@ Example: clocks =3D <&clk IMX8MQ_CLK_DISP_APB_ROOT>; clock-names =3D "ipg"; fsl,channel =3D <0>; - fsl,irq-groups =3D <1>; + fsl,num-irqs =3D <64>; interrupt-controller; #interrupt-cells =3D <1>; }; --=20 2.7.4