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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 95a03f55-c0d2-4a5f-2772-08d68777beb6 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Jan 2019 12:29:16.1106 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB1454 X-OriginatorOrg: microchip.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Claudiu Beznea Add drive strength support for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea --- drivers/pinctrl/pinctrl-at91.c | 52 ++++++++++++++++++++++++++++++++++++++= ++++ drivers/pinctrl/pinctrl-at91.h | 2 ++ 2 files changed, 54 insertions(+) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.= c index 31f06dafca2e..46443b97d811 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -574,6 +574,17 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void= __iomem *pio, return tmp; } =20 +static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio, + unsigned pin) +{ + unsigned tmp =3D readl_relaxed(pio + SAM9X60_PIO_DRIVER1); + + if (tmp & BIT(pin)) + return DRIVE_STRENGTH_BIT_HI; + + return DRIVE_STRENGTH_BIT_LOW; +} + static void set_drive_strength(void __iomem *reg, unsigned pin, u32 streng= th) { unsigned tmp =3D readl_relaxed(reg); @@ -611,6 +622,27 @@ static void at91_mux_sam9x5_set_drivestrength(void __i= omem *pio, unsigned pin, setting); } =20 +static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned= pin, + u32 setting) +{ + unsigned int tmp; + + if (setting <=3D DRIVE_STRENGTH_BIT_DEF || + setting =3D=3D DRIVE_STRENGTH_BIT_MED || + setting > DRIVE_STRENGTH_BIT_HI) + return; + + tmp =3D readl_relaxed(pio + SAM9X60_PIO_DRIVER1); + + /* Strength is 0: low, 1: hi */ + if (setting =3D=3D DRIVE_STRENGTH_BIT_LOW) + tmp &=3D ~BIT(pin); + else + tmp |=3D BIT(pin); + + writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1); +} + static struct at91_pinctrl_mux_ops at91rm9200_ops =3D { .get_periph =3D at91_mux_get_periph, .mux_A_periph =3D at91_mux_set_A_periph, @@ -639,6 +671,26 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops =3D = { .irq_type =3D alt_gpio_irq_type, }; =20 +static const struct at91_pinctrl_mux_ops sam9x60_ops =3D { + .get_periph =3D at91_mux_pio3_get_periph, + .mux_A_periph =3D at91_mux_pio3_set_A_periph, + .mux_B_periph =3D at91_mux_pio3_set_B_periph, + .mux_C_periph =3D at91_mux_pio3_set_C_periph, + .mux_D_periph =3D at91_mux_pio3_set_D_periph, + .get_deglitch =3D at91_mux_pio3_get_deglitch, + .set_deglitch =3D at91_mux_pio3_set_deglitch, + .get_debounce =3D at91_mux_pio3_get_debounce, + .set_debounce =3D at91_mux_pio3_set_debounce, + .get_pulldown =3D at91_mux_pio3_get_pulldown, + .set_pulldown =3D at91_mux_pio3_set_pulldown, + .get_schmitt_trig =3D at91_mux_pio3_get_schmitt_trig, + .disable_schmitt_trig =3D at91_mux_pio3_disable_schmitt_trig, + .get_drivestrength =3D at91_mux_sam9x60_get_drivestrength, + .set_drivestrength =3D at91_mux_sam9x60_set_drivestrength, + .irq_type =3D alt_gpio_irq_type, + +}; + static struct at91_pinctrl_mux_ops sama5d3_ops =3D { .get_periph =3D at91_mux_pio3_get_periph, .mux_A_periph =3D at91_mux_pio3_set_A_periph, diff --git a/drivers/pinctrl/pinctrl-at91.h b/drivers/pinctrl/pinctrl-at91.= h index 79b957f1dfa2..19fc27e66bfd 100644 --- a/drivers/pinctrl/pinctrl-at91.h +++ b/drivers/pinctrl/pinctrl-at91.h @@ -69,4 +69,6 @@ #define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/ #define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/ =20 +#define SAM9X60_PIO_DRIVER1 0x118 /* PIO Driver 1 register offset */ + #endif --=20 2.7.4