From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F19BC282CB for ; Fri, 8 Feb 2019 09:54:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 48AEC21920 for ; Fri, 8 Feb 2019 09:54:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727515AbfBHJy1 (ORCPT ); Fri, 8 Feb 2019 04:54:27 -0500 Received: from metis.ext.pengutronix.de ([85.220.165.71]:59597 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726081AbfBHJy1 (ORCPT ); Fri, 8 Feb 2019 04:54:27 -0500 Received: from kresse.hi.pengutronix.de ([2001:67c:670:100:1d::2a]) by metis.ext.pengutronix.de with esmtp (Exim 4.89) (envelope-from ) id 1gs2rU-0001QD-KN; Fri, 08 Feb 2019 10:54:20 +0100 Message-ID: <1549619660.2544.89.camel@pengutronix.de> Subject: Re: [RFC v2 5/5] arm64: dts: imx8mq-evk: Enable PCIE0 interface From: Lucas Stach To: Andrey Smirnov Cc: Shawn Guo , Fabio Estevam , Chris Healy , Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Fri, 08 Feb 2019 10:54:20 +0100 In-Reply-To: <20190208002941.30343-6-andrew.smirnov@gmail.com> References: <20190208002941.30343-1-andrew.smirnov@gmail.com> <20190208002941.30343-6-andrew.smirnov@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.6-1+deb9u1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::2a X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Donnerstag, den 07.02.2019, 16:29 -0800 schrieb Andrey Smirnov: > Enable PCIE0 interface connected to BCM4356 WiFi/Bluetooth module. > > > Signed-off-by: Andrey Smirnov > Cc: Shawn Guo > Cc: Fabio Estevam > Cc: Chris Healy > Cc: Lucas Stach > Cc: Leonard Crestez > Cc: "A.s. Dong" > Cc: Richard Zhu > Cc: linux-imx@nxp.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > --- >  arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 34 ++++++++++++++++++++ >  1 file changed, 34 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > index 64acccc4bfcb..20afdb9ffdd9 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > @@ -31,6 +31,12 @@ >   gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; >   enable-active-high; >   }; > + > + pcie0_refclk: pcie0-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + }; >  }; >   >  &fec1 { > @@ -40,6 +46,14 @@ > >   status = "okay"; >  }; >   > +&gpio5 { > +  wl-reg-on { > + gpio-hog; > + gpios = <29 GPIO_ACTIVE_HIGH>; > + output-high; > + }; > +}; > + >  &i2c1 { > >   clock-frequency = <100000>; > >   pinctrl-names = "default"; > @@ -131,6 +145,18 @@ > >   }; >  }; >   > +&pcie0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0>; > + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; > + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, > +  <&clk IMX8MQ_CLK_PCIE1_AUX>, > +  <&clk IMX8MQ_CLK_PCIE1_PHY>, > +  <&pcie0_refclk>; > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; > + status = "okay"; > +}; >From a PCIe PoV I think this is fine. Please send a patch for the PCIe driver to use the pcie_aux clock. > + >  &uart1 { >   pinctrl-names = "default"; >   pinctrl-0 = <&pinctrl_uart1>; > @@ -195,6 +221,14 @@ >   >; >   }; >   > + pinctrl_pcie0: pcie0grp { > + fsl,pins = < > + MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 > + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 Shouldn't this GPIO be separated in a pinctrl group for gpio5? > + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 > + >; > + }; > + >   pinctrl_reg_usdhc2: regusdhc2grpgpio { >   fsl,pins = < >   MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41