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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: gu0ueULUJBP3Yvgu2TTt+WIXYbTuHq/KTBnotFKvmIEnj5QWOpGFbhfJ3OOO08lI91VQhV/o6owe8anKfu2Di51iJR9KGefmsL73JeyW12r5cFvfYeEZzpWIq/KCYXmP8UM1oqUKduiYTLRhxqesXdw0I07pjnT9dV+wG5i05vz4UCIMbxw1hC69tEQBfgh8bP0/R4lbsrvfnlg21L9aTcpfWCFZMA25mWeb5y0Io1T07L/mOQUQahMD2HhrGD4IbqoFebtMjdZwsEYm9j23SZLj+taYS4BK9iUuTBCqgmm+lXpyXENoCBKo0RtH129pcAeSk+xOruZ03GGTtPt7/+kmzzTZp1FvD+wntHDnF+K0lQrdmtE1pYJ6tlzltGRutrCArsnuH0a/+tB87RMLoe83b40kXXnOD0/ogFThcHo= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a92e9921-6880-4435-cc9f-08d6932701bd X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Feb 2019 09:21:43.6589 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3615 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sanjay R Mehta As per amd ntb spec it says that peer limit register must be programmed Signed-off-by: Sanjay R Mehta --- drivers/ntb/hw/amd/ntb_hw_amd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_am= d.c index efb214f..cd463e1 100644 --- a/drivers/ntb/hw/amd/ntb_hw_amd.c +++ b/drivers/ntb/hw/amd/ntb_hw_amd.c @@ -160,8 +160,8 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, in= t pidx, int idx, } =20 /* set and verify setting the limit */ - write64(limit, mmio + limit_reg); - reg_val =3D read64(mmio + limit_reg); + write64(limit, peer_mmio + limit_reg); + reg_val =3D read64(peer_mmio + limit_reg); if (reg_val !=3D limit) { write64(base_addr, mmio + limit_reg); write64(0, peer_mmio + xlat_reg); @@ -183,8 +183,8 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, in= t pidx, int idx, } =20 /* set and verify setting the limit */ - writel(limit, mmio + limit_reg); - reg_val =3D readl(mmio + limit_reg); + writel(limit, peer_mmio + limit_reg); + reg_val =3D readl(peer_mmio + limit_reg); if (reg_val !=3D limit) { writel(base_addr, mmio + limit_reg); writel(0, peer_mmio + xlat_reg); --=20 2.7.4