Re: [Lse-tech] Re: 10.31 second kernel compile

[David Mosberger <davidm@napali.hpl.hp.com>]

>>>>> On Sat, 16 Mar 2002 11:58:22 -0800 (PST), Linus Torvalds <torvalds@transmeta.com> said:

  Linus> I used to be a sw fill proponent, but I've grown personally
  Linus> convinced that while sw fill is good, it needs a few things:

Glad to see you're coming around! ;-)

  Linus>  - large on-chip TLB to avoid excessive trashing (ie
  Linus> preferably thousands of entries)

  Linus>    This implies that the TLB should be split into a L1 and a
  Linus> L2, for all the same reasons you split other caches that way
  Linus> (and with the L1 probably being duplicated among all memory
  Linus> units)

Yes, Itanium has a two-level DTLB, McKinley has both ITLB and DTLB
split into two levels.  Not quite as big though: "only" on the order
of hundreds of entries (partially offset by larger page sizes).  Of
course, operating the hardware walker in hashed mode can give you an
L3 TLB as large as you want it to be.

  Linus>  - ability to fill multiple entries in one go to offset the
  Linus> cost of taking the trap.

The software fill can definitely do that.  I think it's one area where
some interesting experimentation could happen.

	--david