From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E36ABC4360F for ; Thu, 21 Feb 2019 16:11:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B43852083E for ; Thu, 21 Feb 2019 16:11:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728167AbfBUQLR (ORCPT ); Thu, 21 Feb 2019 11:11:17 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:30073 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725880AbfBUQLR (ORCPT ); Thu, 21 Feb 2019 11:11:17 -0500 X-IronPort-AV: E=Sophos;i="5.58,395,1544454000"; d="scan'208";a="8500145" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 22 Feb 2019 01:11:14 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6BED140A6A10; Fri, 22 Feb 2019 01:11:11 +0900 (JST) From: Gareth Williams To: Rob Herring , Mark Rutland , Alexandre Belloni , Wolfram Sang , Jarkko Nikula , Andy Shevchenko , Mika Westerberg Cc: Gareth Williams , devicetree@vger.kernel.org, linux-i2c@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Phil Edworthy Subject: [PATCH v4 0/2] i2c: designware: Add support for a bus clock Date: Thu, 21 Feb 2019 16:10:57 +0000 Message-Id: <1550765459-14519-1-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Synopsys I2C Controller has a peripheral clock that some SoCs require to access the registers. This series also details the new clock property in the bindings documentation. v4: - Code comments and commit messages updated to reference "peripheral clock" instead of "bus clock". - Rebased onto next-20190221. v3: - busclk renamed to pclk. - Added comment with dw_i2c_dev struct definition describing pclk. - Added enable rollback of first clock if second fails to enable. - Changed clocks and clock-names sections to use term "peripheral clock" (pclk) instead of "bus clock" (busclk) in dt-bindings documentation. v2: - Use new devm_clk_get_optional() function as it simplifies handling when the optional clock is not present. Phil Edworthy (2): dt: snps,designware-i2c: Add clock bindings documentation i2c: designware: Add support for a peripheral clock .../devicetree/bindings/i2c/i2c-designware.txt | 9 +++++++++ drivers/i2c/busses/i2c-designware-common.c | 18 ++++++++++++++++-- drivers/i2c/busses/i2c-designware-core.h | 2 ++ drivers/i2c/busses/i2c-designware-platdrv.c | 5 +++++ 4 files changed, 32 insertions(+), 2 deletions(-) -- 2.7.4