From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 542DAC43381 for ; Sat, 2 Mar 2019 05:20:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 21F4020857 for ; Sat, 2 Mar 2019 05:20:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="HPguesaP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727804AbfCBFUf (ORCPT ); Sat, 2 Mar 2019 00:20:35 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9814 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725300AbfCBFUe (ORCPT ); Sat, 2 Mar 2019 00:20:34 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 01 Mar 2019 21:20:42 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 01 Mar 2019 21:20:33 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 01 Mar 2019 21:20:33 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 2 Mar 2019 05:20:33 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sat, 2 Mar 2019 05:20:33 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.134]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 01 Mar 2019 21:20:32 -0800 From: Sowjanya Komatineni To: , , , , CC: , , , , , , , Sowjanya Komatineni Subject: [PATCH V1 02/11] mmc: sdhci: allow host to specify maximum tuning loops Date: Fri, 1 Mar 2019 21:20:16 -0800 Message-ID: <1551504025-3541-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> References: <1551504025-3541-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551504042; bh=+Pp6rIrvJvggoBUpoCHnktYSalCLLDgvrPjVwKSaiBk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=HPguesaPq90KRCy+QMj+2tu2Y1fxuymcaJDRwh5WtNmkx5klQdhAx3+kwKeKL/ObB m+E7n/nFf1LvtdFHT6v7X82fsQDYjvpiB6/nNO+jhEl/45uCs/2nFngi5fZmzMTDTl TqlPTjlAee6x6H2GuzB43gNnxbyFv5YgJLxLku/F6OGlGRPL6wOzGQGFkfiU+IydE7 7s6sa3fWwu2F4kOMRVeHMOU5JcPI18/ZhJvwHKlRrU+UXaeefVHi9UPlYBMed+SBvG QfcNp5EgNaQKfe1HU+QmX+eoxtx2zCteJ+ypKXdr4G7w8g6g3/zw0hxTB2ehb7fJ6t BIUiMkIz4KX8w== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As per the Host Controller Standard Specification Version 4.20, limitation of tuning iteration count is removed as PLL locking time can be longer than UHS-1 tuning due to larger PVT fluctuation and it will result in increase of tuning iteration to complete the tuning. This patch creates a hook get_max_tuning_loop_count to allow hosts to specify maximum tuning iterations and updates execute_tuning to use the specified maximum tuning iteration count. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci.c | 7 +++++-- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index a8141ff9be03..e9e919218006 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2366,12 +2366,15 @@ EXPORT_SYMBOL_GPL(sdhci_send_tuning); static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) { int i; + int tuning_loop_count = MAX_TUNING_LOOP; + if (host->ops->get_max_tuning_loop_count) + tuning_loop_count = host->ops->get_max_tuning_loop_count(host); /* * Issue opcode repeatedly till Execute Tuning is set to 0 or the number - * of loops reaches 40 times. + * of loops reaches tuning loop count. */ - for (i = 0; i < MAX_TUNING_LOOP; i++) { + for (i = 0; i < tuning_loop_count; i++) { u16 ctrl; sdhci_send_tuning(host, opcode); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 01002cba1359..c80e0d6f9b10 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -638,6 +638,7 @@ struct sdhci_ops { unsigned int (*get_ro)(struct sdhci_host *host); void (*reset)(struct sdhci_host *host, u8 mask); int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); + int (*get_max_tuning_loop_count)(struct sdhci_host *host); void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); void (*hw_reset)(struct sdhci_host *host); void (*adma_workaround)(struct sdhci_host *host, u32 intmask); -- 2.7.4