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[193.116.74.175]) by smtp.gmail.com with ESMTPSA id m20sm5798295pfj.142.2019.03.03.02.05.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Mar 2019 02:05:30 -0800 (PST) Date: Sun, 03 Mar 2019 20:05:23 +1000 From: Nicholas Piggin Subject: Re: [PATCH 01/20] asm-generic/mmiowb: Add generic implementation of mmiowb() tracking To: Linus Torvalds Cc: Andrea Parri , Arnd Bergmann , Benjamin Herrenschmidt , Rich Felker , David Howells , Daniel Lustig , linux-arch , Linux List Kernel Mailing , "Maciej W. Rozycki" , Ingo Molnar , Michael Ellerman , Palmer Dabbelt , Paul Burton , "Paul E. McKenney" , Peter Zijlstra , Alan Stern , Tony Luck , Will Deacon , Yoshinori Sato References: <20190301140348.25175-1-will.deacon@arm.com> <20190301140348.25175-2-will.deacon@arm.com> <1551575210.6lwpiqtg5k.astroid@bobo.none> <1551583190.duzqnmfnvg.astroid@bobo.none> In-Reply-To: MIME-Version: 1.0 User-Agent: astroid/0.14.0 (https://github.com/astroidmail/astroid) Message-Id: <1551606848.8cceyn7nhv.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Linus Torvalds's on March 3, 2019 2:29 pm: > On Sat, Mar 2, 2019, 19:34 Nicholas Piggin wrote: >=20 >> >> It doesn't have to be done all at once with this series, obviously this >> is a big improvement on its own. But why perpetuate the nomenclature >> and concept for new code added now? >> >=20 > What nomenclature? >=20 > Nobody will be using mmiowb(). That's the whole point of the patch series= . >=20 > It's now an entirely internal name, and nobody cares. Why even bother with it at all, "internal" or not? Just get rid of=20 mmiowb, the concept is obsolete. > And none of this has anything to do with wmb(), since it's about IO being > ordered across cpu's by spin locks, not by barriers. >=20 > So I'm not seeing what you're arguing about. Pretend ia64 doesn't exist for a minute. Now the regular mb/wmb barriers=20 orders IO across CPUs with respect to their cacheable accesses. =20 Regardless of whether that cacheable access is a spin lock, a bit lock,=20 an atomic, a mutex... This is how it was before mmiowb came along. Nothing wrong with this series to make spinlocks order mmio, but why=20 call it mmiowb? Another patch could rename ia64's mmiowb and then the name can be removed from the tree completely. Thanks, Nick =