From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 866F1C4360F for ; Tue, 12 Mar 2019 08:46:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5671D214AE for ; Tue, 12 Mar 2019 08:46:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nifty.com header.i=@nifty.com header.b="OON98J3F" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727638AbfCLIqp (ORCPT ); Tue, 12 Mar 2019 04:46:45 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:37467 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726560AbfCLIqm (ORCPT ); Tue, 12 Mar 2019 04:46:42 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id x2C8j6Zi004092; Tue, 12 Mar 2019 17:45:22 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com x2C8j6Zi004092 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1552380322; bh=mQR7r33kBKitXzpLskswUugSgJVShOOSmdtp2U7FsBI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OON98J3FEZh2Hac6J3ryrNkBWKlixGE5hrR/QiFztrKdj6rCq9lLwnv26WQIwELj5 BGmAq+P00Gdp2Fp7YytELfpeyjqvVECZ/eriemWyCZUVOjaSCaW8//qPMRRiziOtan UPYNmYa5HvLe1tVAU8jASrOJk98zAonzc2E+SmEyW42APZ/87f/KHlwIgNHa182yIP G8zhl6udnZwEGut/FlYHS4qkYYuskWNtDuVDlH1ztTxGl6gT1/26TEVUYkwCjSDyyw mQWPmGstMSuWR1geG9w4TKfiDskowoZVbBjhROfmpv4/s4NhpnA3LNCb2gVk2QH49M 6YcN6UVsdT9bw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Miquel Raynal Cc: Boris Brezillon , Masahiro Yamada , Brian Norris , linux-kernel@vger.kernel.org, Marek Vasut , Richard Weinberger , David Woodhouse Subject: [PATCH v3 8/9] mtd: rawnand: denali: remove DENALI_NR_BANKS macro Date: Tue, 12 Mar 2019 17:44:49 +0900 Message-Id: <1552380290-19951-9-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552380290-19951-1-git-send-email-yamada.masahiro@socionext.com> References: <1552380290-19951-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use the runtime-detected denali->nbanks instead of hard-coded DENALI_NR_BANKS (=4). The actual number of banks depends on the IP configuration, and can be less than DENALI_NR_BANKS. It is pointless to touch registers of unsupported banks. Signed-off-by: Masahiro Yamada --- Changes in v3: None Changes in v2: None drivers/mtd/nand/raw/denali.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index 0c47c56..b1a4d9c 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -40,7 +40,6 @@ #define DENALI_BANK(denali) ((denali)->active_bank << 24) #define DENALI_INVALID_BANK -1 -#define DENALI_NR_BANKS 4 static struct denali_chip *to_denali_chip(struct nand_chip *chip) { @@ -92,7 +91,7 @@ static void denali_enable_irq(struct denali_controller *denali) { int i; - for (i = 0; i < DENALI_NR_BANKS; i++) + for (i = 0; i < denali->nbanks; i++) iowrite32(U32_MAX, denali->reg + INTR_EN(i)); iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); } @@ -101,7 +100,7 @@ static void denali_disable_irq(struct denali_controller *denali) { int i; - for (i = 0; i < DENALI_NR_BANKS; i++) + for (i = 0; i < denali->nbanks; i++) iowrite32(0, denali->reg + INTR_EN(i)); iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); } @@ -117,7 +116,7 @@ static void denali_clear_irq_all(struct denali_controller *denali) { int i; - for (i = 0; i < DENALI_NR_BANKS; i++) + for (i = 0; i < denali->nbanks; i++) denali_clear_irq(denali, i, U32_MAX); } @@ -130,7 +129,7 @@ static irqreturn_t denali_isr(int irq, void *dev_id) spin_lock(&denali->irq_lock); - for (i = 0; i < DENALI_NR_BANKS; i++) { + for (i = 0; i < denali->nbanks; i++) { irq_status = ioread32(denali->reg + INTR_STATUS(i)); if (irq_status) ret = IRQ_HANDLED; -- 2.7.4