From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<talho@nvidia.com>, <skomatineni@nvidia.com>,
<broonie@kernel.org>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <kyarlagadda@nvidia.com>
Cc: <ldewangan@nvidia.com>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>,
<devicetree@vger.kernel.org>
Subject: [PATCH V2 05/20] spi: tegra114: dump SPI registers during timeout
Date: Thu, 4 Apr 2019 17:14:04 -0700 [thread overview]
Message-ID: <1554423259-26056-5-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1554423259-26056-1-git-send-email-skomatineni@nvidia.com>
This patch dumps SPI registers on transfer error or timeout for debug
purpose.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/spi/spi-tegra114.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index d928a2c92a3d..e0f20fad5df2 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -876,6 +876,20 @@ static void tegra_spi_transfer_end(struct spi_device *spi)
tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
}
+static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
+{
+ dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
+ dev_dbg(tspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n",
+ tegra_spi_readl(tspi, SPI_COMMAND1),
+ tegra_spi_readl(tspi, SPI_COMMAND2));
+ dev_dbg(tspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n",
+ tegra_spi_readl(tspi, SPI_DMA_CTL),
+ tegra_spi_readl(tspi, SPI_DMA_BLK));
+ dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n",
+ tegra_spi_readl(tspi, SPI_TRANS_STATUS),
+ tegra_spi_readl(tspi, SPI_FIFO_STATUS));
+}
+
static int tegra_spi_transfer_one_message(struct spi_master *master,
struct spi_message *msg)
{
@@ -922,6 +936,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
(tspi->cur_direction & DATA_DIR_RX))
dmaengine_terminate_all(tspi->rx_dma_chan);
ret = -EIO;
+ tegra_spi_dump_regs(tspi);
tegra_spi_flush_fifos(tspi);
reset_control_assert(tspi->rst);
udelay(2);
@@ -932,6 +947,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
if (tspi->tx_status || tspi->rx_status) {
dev_err(tspi->dev, "Error in Transfer\n");
ret = -EIO;
+ tegra_spi_dump_regs(tspi);
goto complete_xfer;
}
msg->actual_length += xfer->len;
@@ -973,6 +989,7 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
tspi->status_reg);
dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
tspi->command1_reg, tspi->dma_control_reg);
+ tegra_spi_dump_regs(tspi);
tegra_spi_flush_fifos(tspi);
complete(&tspi->xfer_completion);
spin_unlock_irqrestore(&tspi->lock, flags);
@@ -1047,6 +1064,7 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
tspi->status_reg);
dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
tspi->command1_reg, tspi->dma_control_reg);
+ tegra_spi_dump_regs(tspi);
tegra_spi_flush_fifos(tspi);
complete(&tspi->xfer_completion);
spin_unlock_irqrestore(&tspi->lock, flags);
--
2.7.4
next prev parent reply other threads:[~2019-04-05 0:15 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-05 0:14 [PATCH V2 01/20] spi: tegra114: fix PIO transfer Sowjanya Komatineni
2019-04-05 0:14 ` [PATCH V2 02/20] spi: tegra114: use unpacked mode for below 4 bytes Sowjanya Komatineni
2019-04-05 0:14 ` [PATCH V2 03/20] spi: tegra114: de-assert CS before SPI mode change Sowjanya Komatineni
2019-04-05 3:27 ` Applied "spi: tegra114: de-assert CS before SPI mode change" to the spi tree Mark Brown
2019-04-05 0:14 ` [PATCH V2 04/20] spi: tegra114: avoid reset call in atomic context Sowjanya Komatineni
2019-04-05 3:26 ` Applied "spi: tegra114: avoid reset call in atomic context" to the spi tree Mark Brown
2019-04-05 0:14 ` Sowjanya Komatineni [this message]
2019-04-05 3:26 ` Applied "spi: tegra114: dump SPI registers during timeout" " Mark Brown
2019-04-05 0:14 ` [PATCH V2 06/20] spi: tegra114: set supported bits per word Sowjanya Komatineni
2019-04-05 3:26 ` Applied "spi: tegra114: set supported bits per word" to the spi tree Mark Brown
2019-04-05 0:14 ` [PATCH V2 07/20] spi: tegra114: set bus number based on id Sowjanya Komatineni
2019-04-05 0:14 ` [PATCH V2 08/20] spi: tegra114: add dual mode support Sowjanya Komatineni
2019-04-08 7:32 ` Applied "spi: tegra114: add dual mode support" to the spi tree Mark Brown
2019-04-05 0:14 ` [PATCH V2 09/20] spi: tegra114: add 3 wire transfer mode support Sowjanya Komatineni
2019-04-08 7:31 ` Applied "spi: tegra114: add 3 wire transfer mode support" to the spi tree Mark Brown
2019-04-05 0:14 ` [PATCH V2 10/20] Documentation: devicetree: spi: add spi-lsbyte-first propery Sowjanya Komatineni
2019-04-08 6:27 ` Mark Brown
2019-04-05 0:14 ` [PATCH V2 11/20] spi: expand mode support and add LSBYTE_FIRST mode Sowjanya Komatineni
2019-04-08 6:28 ` Mark Brown
2019-04-11 19:58 ` Sowjanya Komatineni
2019-04-12 8:32 ` Mark Brown
2019-04-05 0:14 ` [PATCH V2 12/20] spi: tegra114: add support for LSBYTE_FIRST Sowjanya Komatineni
2019-04-05 0:14 ` [PATCH V2 13/20] spi: tegra114: add support for interrupt mask Sowjanya Komatineni
2019-04-05 0:14 ` [PATCH V2 14/20] spi: tegra114: add support for gpio based cs Sowjanya Komatineni
2019-04-08 6:30 ` Mark Brown
2019-04-05 0:14 ` [PATCH V2 15/20] spi: tegra114: add support for hw " Sowjanya Komatineni
2019-04-05 0:14 ` [PATCH V2 16/20] spi-summary: document set_cs_timing Sowjanya Komatineni
2019-04-08 7:31 ` Applied "spi-summary: document set_cs_timing" to the spi tree Mark Brown
2019-04-05 0:14 ` [PATCH V2 17/20] spi: add a method for configuring CS timing Sowjanya Komatineni
2019-04-08 7:31 ` Applied "spi: add a method for configuring CS timing" to the spi tree Mark Brown
2019-04-05 0:14 ` [PATCH V2 18/20] spi: tegra114: add support for HW CS timing Sowjanya Komatineni
2019-04-05 0:14 ` [PATCH V2 19/20] DT bindings: spi: document tx/rx clock delay properties Sowjanya Komatineni
2019-04-08 7:22 ` Mark Brown
2019-04-08 7:31 ` Applied "spi: document tx/rx clock delay properties" to the spi tree Mark Brown
2019-04-05 0:14 ` [PATCH V2 20/20] spi: tegra114: add support for tuning TX and RX trimmers Sowjanya Komatineni
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