From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B453C10F0E for ; Mon, 15 Apr 2019 21:31:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 668C42070D for ; Mon, 15 Apr 2019 21:31:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="H70k9RoO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728055AbfDOVb0 (ORCPT ); Mon, 15 Apr 2019 17:31:26 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:16535 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728242AbfDOVax (ORCPT ); Mon, 15 Apr 2019 17:30:53 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 15 Apr 2019 14:30:58 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 15 Apr 2019 14:30:52 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 15 Apr 2019 14:30:52 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 15 Apr 2019 21:30:51 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 15 Apr 2019 21:30:51 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.253]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 15 Apr 2019 14:30:51 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V3 4/9] spi: tegra114: add support for Tegra SPI LSBYTE_FIRST Date: Mon, 15 Apr 2019 14:30:29 -0700 Message-ID: <1555363834-32155-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555363834-32155-1-git-send-email-skomatineni@nvidia.com> References: <1555363834-32155-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555363858; bh=cpSMZ14Olne7ZCx8UfGZqwMXyKIGuNnvzCASpqQU17A=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=H70k9RoOvUN2RAerXzkzcIHTi9l2qt7ZcMfvx47z48JoFJUrU8cOfokK0bkhgIyio Sq/Tr8Xo/KnxKb8LDoaMAyXdqc7E3/jikzk6Djd1FIPkbipc0O86+vhw/zIXVyW4yi lOw7E0tjJe5aY/lbCuRAXHAK+CobdGS8fPs6SXfRr68axyfZoPgyyhTXMulkat93fv q2mM9tnm0gxaARhZD9IRZFRsL0fGZBIA949L+r889UHFpMQRKOeuZcBwi8H3F7/H03 feanpHPs5fjx0D4xCYE0mSy2vbCmOHYnFL+kZ1RL4O9orRYstjSGGtrcp5zP5COXUT FvcUqRVGIC+Cw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra SPI master controller supports configuring least significant first byte order or most significant first byte order for transfers. This patch adds SPI_LSBYTE_FIRST to supported mode list and also configures byte order based on the mode request for transfer. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index b1f31bb16659..f4e39eb3857c 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -764,6 +764,11 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, else command1 &= ~SPI_LSBIT_FE; + if (spi->mode & SPI_LSBYTE_FIRST) + command1 |= SPI_LSBYTE_FE; + else + command1 &= ~SPI_LSBYTE_FE; + if (spi->mode & SPI_3WIRE) command1 |= SPI_BIDIROE; else @@ -1200,7 +1205,8 @@ static int tegra_spi_probe(struct platform_device *pdev) /* the spi->mode bits understood by this driver: */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | - SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE; + SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE | + SPI_LSBYTE_FIRST; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); master->setup = tegra_spi_setup; master->transfer_one_message = tegra_spi_transfer_one_message; -- 2.7.4