From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85ECEC10F13 for ; Tue, 16 Apr 2019 09:30:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5371220651 for ; Tue, 16 Apr 2019 09:30:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729206AbfDPJa1 (ORCPT ); Tue, 16 Apr 2019 05:30:27 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:7680 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729069AbfDPJaZ (ORCPT ); Tue, 16 Apr 2019 05:30:25 -0400 X-UUID: f426339a14734be19177173866ae87b8-20190416 X-UUID: f426339a14734be19177173866ae87b8-20190416 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 258693429; Tue, 16 Apr 2019 17:30:19 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 16 Apr 2019 17:30:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 16 Apr 2019 17:30:18 +0800 From: Stu Hsieh To: Mauro Carvalho Chehab , Rob Herring , CK Hu CC: Mark Rutland , Matthias Brugger , Stu Hsieh , , , , , , Subject: [PATCH v2 09/15] [media] mtk-mipicsi: enable/disable cmos for mt2712 Date: Tue, 16 Apr 2019 17:30:09 +0800 Message-ID: <1555407015-18130-10-git-send-email-stu.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555407015-18130-1-git-send-email-stu.hsieh@mediatek.com> References: <1555407015-18130-1-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch enable/disable cmos setting for mt2712 when vb2 start/stop streaming. Signed-off-by: Stu Hsieh --- .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c index 8a4079f0ed9b..7331543d400a 100644 --- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c +++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c @@ -97,9 +97,11 @@ #define CAMSV_MODULE_EN 0x10 #define CAMSV_FMT_SEL 0x14 #define CAMSV_INT_EN 0x18 +#define CAMSV_SW_CTL 0x20 #define CAMSV_CLK_EN 0x30 #define CAMSV_TG_SEN_MODE 0x500 +#define CAMSV_TG_VF_CON 0x504 #define CAMSV_TG_SEN_GRAB_PXL 0x508 #define CAMSV_TG_SEN_GRAB_LIN 0x50C #define CAMSV_TG_PATH_CFG 0x510 @@ -531,9 +533,25 @@ static int mtk_mipicsi_vb2_start_streaming(struct vb2_queue *vq, struct soc_camera_device *icd = soc_camera_from_vb2q(vq); struct soc_camera_host *ici = to_soc_camera_host(icd->parent); struct mtk_mipicsi_dev *mipicsi = ici->priv; + unsigned int index = 0; + void __iomem *base = NULL; icd->vdev->queue = vq; + for (index = 0U; index < MTK_CAMDMA_MAX_NUM; ++index) + if (((mipicsi->link_reg_val >> index) & 0x01U) == 0x01U && + !mipicsi->is_enable_irq[index]) { + enable_irq(mipicsi->irq[index]); + mipicsi->is_enable_irq[index] = true; + + /*enable cmos_en and vf_en*/ + base = mipicsi->camsv[index]; + writel(0x00000001U | readl(base + CAMSV_TG_SEN_MODE), + base + CAMSV_TG_SEN_MODE); + writel(0x00000001U | readl(base + CAMSV_TG_VF_CON), + base + CAMSV_TG_VF_CON); + } + mipicsi->streamon = true; return 0; } @@ -543,7 +561,29 @@ static void mtk_mipicsi_vb2_stop_streaming(struct vb2_queue *vq) struct mtk_mipicsi_dev *mipicsi = vb2_get_drv_priv(vq); struct mtk_mipicsi_buf *buf = NULL; struct mtk_mipicsi_buf *tmp = NULL; + unsigned int i = 0U; unsigned int index = 0; + void __iomem *base = NULL; + + for (i = 0U; i < MTK_CAMDMA_MAX_NUM; ++i) + if (((mipicsi->link_reg_val >> i) & 0x01U) == 0x01U) { + /*disable cmos_en and vf_en*/ + base = mipicsi->camsv[i]; + writel(readl(base + CAMSV_TG_SEN_MODE) & 0xFFFFFFFEU, + base + CAMSV_TG_SEN_MODE); + writel(readl(base + CAMSV_TG_VF_CON) & 0xFFFFFFFEU, + base + CAMSV_TG_VF_CON); + /*camsv reset*/ + base = mipicsi->camsv[i]; + writel(0x00000004U | readl(base + CAMSV_SW_CTL), + base + CAMSV_SW_CTL); + writel(readl(base + CAMSV_SW_CTL) & 0xFFFFFFFBU, + base + CAMSV_SW_CTL); + disable_irq(mipicsi->irq[i]); + mipicsi->is_enable_irq[i] = false; + mipicsi->frame_cnt[i] = 0UL; + mipicsi->irq_status[i] = false; + } spin_lock(&mipicsi->queue_lock); while (list_empty(&(mipicsi->fb_list)) == 0) { -- 2.18.0