From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42C02C004C9 for ; Wed, 8 May 2019 02:59:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0BF2121019 for ; Wed, 8 May 2019 02:59:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726714AbfEHC70 (ORCPT ); Tue, 7 May 2019 22:59:26 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:47823 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726448AbfEHC7Z (ORCPT ); Tue, 7 May 2019 22:59:25 -0400 X-UUID: a4a81512090942aaac24d180c54b5cf8-20190508 X-UUID: a4a81512090942aaac24d180c54b5cf8-20190508 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1494308194; Wed, 08 May 2019 10:59:16 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 8 May 2019 10:59:15 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 8 May 2019 10:59:15 +0800 Message-ID: <1557284354.31731.9.camel@mtksdaap41> Subject: Re: [v2 4/5] drm/mediatek: add frame size control From: CK Hu To: Jitao Shi CC: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , Kumar Gala , , David Airlie , "Matthias Brugger" , Thierry Reding , "Ajay Kumar" , Inki Dae , "Rahul Sharma" , Sean Paul , Vincent Palatin , Andy Yan , Philipp Zabel , "Russell King" , , , , , , , Sascha Hauer , , , , , Date: Wed, 8 May 2019 10:59:14 +0800 In-Reply-To: <20190416060501.76276-5-jitao.shi@mediatek.com> References: <20190416060501.76276-1-jitao.shi@mediatek.com> <20190416060501.76276-5-jitao.shi@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Jitao: On Tue, 2019-04-16 at 14:05 +0800, Jitao Shi wrote: > Our new DSI chip has frame size control. > So add the driver data to control for different chips. > Reviewed-by: CK Hu > Signed-off-by: Jitao Shi > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index be42405a0a78..458a700ce74c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -78,6 +78,7 @@ > #define DSI_VBP_NL 0x24 > #define DSI_VFP_NL 0x28 > #define DSI_VACT_NL 0x2C > +#define DSI_SIZE_CON 0x38 > #define DSI_HSA_WC 0x50 > #define DSI_HBP_WC 0x54 > #define DSI_HFP_WC 0x58 > @@ -162,6 +163,7 @@ struct phy; > struct mtk_dsi_driver_data { > const u32 reg_cmdq_off; > bool has_shadow_ctl; > + bool has_size_ctl; > }; > > struct mtk_dsi { > @@ -430,6 +432,9 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) > writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL); > writel(vm->vactive, dsi->regs + DSI_VACT_NL); > > + if (dsi->driver_data->has_size_ctl) > + writel(vm->vactive << 16 | vm->hactive, dsi->regs + DSI_SIZE_CON); > + > horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); > > if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)