From: Krishna Yarlagadda <kyarlagadda@nvidia.com>
To: <linus.walleij@linaro.org>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <linux-kernel@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<devicetree@vger.kernel.org>
Cc: <pdeschrijver@nvidia.com>, <josephl@nvidia.com>,
<smangipudi@nvidia.com>, <ldewangan@nvidia.com>,
<vidyas@nvidia.com>, Krishna Yarlagadda <kyarlagadda@nvidia.com>
Subject: [Patch-V2 4/4] soc/tegra: select pinctrl for Tegra194
Date: Thu, 9 May 2019 13:38:16 +0530 [thread overview]
Message-ID: <1557389296-10257-4-git-send-email-kyarlagadda@nvidia.com> (raw)
In-Reply-To: <1557389296-10257-1-git-send-email-kyarlagadda@nvidia.com>
Select PINCTRL_TEGRA194 by default for Tegra194 SOC needed
for dynamically controlling PCIe pins
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
drivers/soc/tegra/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index a0b0344..6f0df55 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -108,6 +108,7 @@ config ARCH_TEGRA_186_SOC
config ARCH_TEGRA_194_SOC
bool "NVIDIA Tegra194 SoC"
select MAILBOX
+ select PINCTRL_TEGRA194
select TEGRA_BPMP
select TEGRA_HSP_MBOX
select TEGRA_IVC
--
2.7.4
next prev parent reply other threads:[~2019-05-09 8:09 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-09 8:08 [Patch-V2 1/4] dt-binding: Tegra194 pinctrl support Krishna Yarlagadda
2019-05-09 8:08 ` [Patch-V2 2/4] pinctrl: tegra: Support 32 bit register access Krishna Yarlagadda
2019-05-09 8:08 ` [Patch-V2 3/4] pinctrl: tegra: Add Tegra194 pinmux driver Krishna Yarlagadda
2019-05-09 8:08 ` Krishna Yarlagadda [this message]
2019-05-09 9:41 ` [Patch-V2 1/4] dt-binding: Tegra194 pinctrl support Jon Hunter
2019-05-09 10:27 ` Krishna Yarlagadda
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