From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B345CC04AB4 for ; Tue, 14 May 2019 06:14:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8E497208CA for ; Tue, 14 May 2019 06:14:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726565AbfENGOR (ORCPT ); Tue, 14 May 2019 02:14:17 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:11083 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726336AbfENGOH (ORCPT ); Tue, 14 May 2019 02:14:07 -0400 X-UUID: c75cdfa19e0a48d78f233b36eefdac77-20190514 X-UUID: c75cdfa19e0a48d78f233b36eefdac77-20190514 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1333107968; Tue, 14 May 2019 14:13:56 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 14 May 2019 14:13:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 14 May 2019 14:13:55 +0800 From: Stu Hsieh To: Mauro Carvalho Chehab , Rob Herring , CK Hu CC: Mark Rutland , Matthias Brugger , Stu Hsieh , , , , , , Subject: [PATCH v3 08/13] [media] mtk-mipicsi: enable/disable cmos for mt2712 Date: Tue, 14 May 2019 14:13:45 +0800 Message-ID: <1557814430-9675-9-git-send-email-stu.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1557814430-9675-1-git-send-email-stu.hsieh@mediatek.com> References: <1557814430-9675-1-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 558BA277E6BA11A095170773E590F33E40DB95F87C438BAB3F404F9A024F06CC2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch enable/disable cmos setting for mt2712 when vb2 start/stop streaming. Signed-off-by: Stu Hsieh --- .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c index f9123765ebbd..44c01c8d566b 100644 --- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c +++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c @@ -93,9 +93,11 @@ #define CAMSV_MODULE_EN 0x10 #define CAMSV_FMT_SEL 0x14 #define CAMSV_INT_EN 0x18 +#define CAMSV_SW_CTL 0x20 #define CAMSV_CLK_EN 0x30 #define CAMSV_TG_SEN_MODE 0x500 +#define CAMSV_TG_VF_CON 0x504 #define CAMSV_TG_SEN_GRAB_PXL 0x508 #define CAMSV_TG_SEN_GRAB_LIN 0x50C #define CAMSV_TG_PATH_CFG 0x510 @@ -518,9 +520,25 @@ static int mtk_mipicsi_vb2_start_streaming(struct vb2_queue *vq, struct soc_camera_device *icd = soc_camera_from_vb2q(vq); struct soc_camera_host *ici = to_soc_camera_host(icd->parent); struct mtk_mipicsi_dev *mipicsi = ici->priv; + unsigned int index = 0; + void __iomem *base = NULL; icd->vdev->queue = vq; + for (index = 0U; index < MTK_CAMDMA_MAX_NUM; ++index) + if (((mipicsi->link_reg_val >> index) & 0x01U) == 0x01U && + !mipicsi->is_enable_irq[index]) { + enable_irq(mipicsi->irq[index]); + mipicsi->is_enable_irq[index] = true; + + /*enable cmos_en and vf_en*/ + base = mipicsi->camsv[index]; + writel(0x00000001U | readl(base + CAMSV_TG_SEN_MODE), + base + CAMSV_TG_SEN_MODE); + writel(0x00000001U | readl(base + CAMSV_TG_VF_CON), + base + CAMSV_TG_VF_CON); + } + mipicsi->streamon = true; return 0; } @@ -530,7 +548,28 @@ static void mtk_mipicsi_vb2_stop_streaming(struct vb2_queue *vq) struct mtk_mipicsi_dev *mipicsi = vb2_get_drv_priv(vq); struct mtk_mipicsi_buf *buf = NULL; struct mtk_mipicsi_buf *tmp = NULL; + unsigned int i = 0U; unsigned int index = 0; + void __iomem *base = NULL; + + for (i = 0U; i < MTK_CAMDMA_MAX_NUM; ++i) + if (((mipicsi->link_reg_val >> i) & 0x01U) == 0x01U) { + /*disable cmos_en and vf_en*/ + base = mipicsi->camsv[i]; + writel(readl(base + CAMSV_TG_SEN_MODE) & 0xFFFFFFFEU, + base + CAMSV_TG_SEN_MODE); + writel(readl(base + CAMSV_TG_VF_CON) & 0xFFFFFFFEU, + base + CAMSV_TG_VF_CON); + /*camsv reset*/ + base = mipicsi->camsv[i]; + writel(0x00000004U | readl(base + CAMSV_SW_CTL), + base + CAMSV_SW_CTL); + writel(readl(base + CAMSV_SW_CTL) & 0xFFFFFFFBU, + base + CAMSV_SW_CTL); + disable_irq(mipicsi->irq[i]); + mipicsi->is_enable_irq[i] = false; + mipicsi->irq_status[i] = false; + } spin_lock(&mipicsi->queue_lock); while (list_empty(&(mipicsi->fb_list)) == 0) { -- 2.18.0