From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0270AC072B5 for ; Fri, 24 May 2019 15:30:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BD79221848 for ; Fri, 24 May 2019 15:30:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="Zqi5Vc3c" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389778AbfEXPa6 (ORCPT ); Fri, 24 May 2019 11:30:58 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:4878 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2389292AbfEXPa5 (ORCPT ); Fri, 24 May 2019 11:30:57 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4OFIB91024824; Fri, 24 May 2019 17:30:45 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=STMicroelectronics; bh=1jp/DW/DgqpUMUcqYc9weRdFKoeCB+M0/u6IuMnuZB0=; b=Zqi5Vc3ciXeUwWx7S/qnN197gWTBLlvJTqRrEdNRIJJxf2gy+di8qVVOwKQakb5woNjw G0RHy5e9QmZJWlPzPQvPJxT7KryOYynxtpgyEyotHjDDGmrFyH72jlc9CelhyYydTZEF rKzwyHLmJceahzT1NY2oc5oeCz/3wC/UKhPFc+Y/jUJ9F+Eg6Cr/zePVN8Y9MmlZWOoZ zJK69FVGQa5y8hzzGFtEQ6yFlqOPo1pAht76WBxG18Kr5hCqbHgBIBjUD4VVDig0cfRv +3JkzT9Uz/u/+hVFUGOTQjSqZp+JkCjthLsoPVgn1XX6YcThLhMgTQuj5LvePsNlZY6P Gw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2sj774pguq-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 24 May 2019 17:30:45 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4B37931; Fri, 24 May 2019 15:30:44 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1BED24FB9; Fri, 24 May 2019 15:30:44 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.46) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 24 May 2019 17:30:43 +0200 Received: from localhost (10.201.23.31) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 24 May 2019 17:30:43 +0200 From: Erwan Le Ray To: Greg Kroah-Hartman , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue CC: , , , , , Fabrice Gasnier , Erwan Le Ray Subject: [PATCH 1/1] dt-bindings: stm32: serial: Add optional reset Date: Fri, 24 May 2019 17:30:38 +0200 Message-ID: <1558711838-21174-1-git-send-email-erwan.leray@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.31] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-05-24_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org STM32 serial can be reset via reset controller. Add an optional reset property to stm32 usart bindings. Signed-off-by: Erwan Le Ray diff --git a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt index 9d3efed..a6b1948 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt +++ b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt @@ -13,6 +13,7 @@ Required properties: - clocks: The input clock of the USART instance Optional properties: +- resets: Must contain the phandle to the reset controller. - pinctrl: The reference on the pins configuration - st,hw-flow-ctrl: bool flag to enable hardware flow control. - rs485-rts-delay, rs485-rx-during-tx, rs485-rts-active-low, -- 1.9.1