From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7AEBC07542 for ; Mon, 27 May 2019 09:05:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9C7AC2173C for ; Mon, 27 May 2019 09:05:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726716AbfE0JFl (ORCPT ); Mon, 27 May 2019 05:05:41 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:31019 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726492AbfE0JFl (ORCPT ); Mon, 27 May 2019 05:05:41 -0400 X-UUID: 1984a0d3cca947e29193c02e3280f2b4-20190527 X-UUID: 1984a0d3cca947e29193c02e3280f2b4-20190527 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 999682; Mon, 27 May 2019 17:05:20 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 27 May 2019 17:05:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 27 May 2019 17:05:19 +0800 From: Erin Lo To: Matthias Brugger , Rob Herring , Mark Rutland CC: , srv_heupstream , , , , , , , , Mengqi Zhang Subject: [PATCH v11 5/6] arm64: dts: mt8183: add spi node Date: Mon, 27 May 2019 17:04:46 +0800 Message-ID: <1558947887-31084-6-git-send-email-erin.lo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1558947887-31084-1-git-send-email-erin.lo@mediatek.com> References: <1558947887-31084-1-git-send-email-erin.lo@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add spi DTS node to the mt8183 and mt8183-evb. Signed-off-by: Mengqi Zhang Signed-off-by: Erin Lo --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 105 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 78 +++++++++++++++++++++ 2 files changed, 183 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 49909ac..d8e555c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -30,6 +30,111 @@ status = "okay"; }; +&pio { + spi_pins_0: spi0{ + pins_spi{ + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi_pins_1: spi1{ + pins_spi{ + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi_pins_2: spi2{ + pins_spi{ + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi_pins_3: spi3{ + pins_spi{ + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi_pins_4: spi4{ + pins_spi{ + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi_pins_5: spi5{ + pins_spi{ + pinmux = , + , + , + ; + bias-disable; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_0>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_1>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_2>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi3 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_3>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_4>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi5 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_5>; + mediatek,pad-select = <0>; + status = "okay"; + +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5672c18..2e3063f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -285,6 +285,84 @@ status = "disabled"; }; + spi0: spi@1100a000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + audiosys: syscon@11220000 { compatible = "mediatek,mt8183-audiosys", "syscon"; reg = <0 0x11220000 0 0x1000>; -- 1.8.1.1.dirty