From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 261F2C282CE for ; Tue, 4 Jun 2019 10:12:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0675024C32 for ; Tue, 4 Jun 2019 10:12:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727322AbfFDKMP (ORCPT ); Tue, 4 Jun 2019 06:12:15 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:16528 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727110AbfFDKMI (ORCPT ); Tue, 4 Jun 2019 06:12:08 -0400 X-UUID: 913cc3a306454d96b3044610a02c493d-20190604 X-UUID: 913cc3a306454d96b3044610a02c493d-20190604 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1893859149; Tue, 04 Jun 2019 18:12:02 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Jun 2019 18:12:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 4 Jun 2019 18:12:01 +0800 From: Stu Hsieh To: Mauro Carvalho Chehab , Rob Herring , CK Hu CC: Mark Rutland , Matthias Brugger , Stu Hsieh , , , , , , Subject: [PATCH v4 10/14] [media] mtk-mipicsi: set the output address in HW reg Date: Tue, 4 Jun 2019 18:11:51 +0800 Message-ID: <1559643115-15124-11-git-send-email-stu.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1559643115-15124-1-git-send-email-stu.hsieh@mediatek.com> References: <1559643115-15124-1-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch set the output address in HW reg when buffer queue and ISR. Signed-off-by: Stu Hsieh --- .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c index dc5c5c888914..9e45786a0282 100644 --- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c +++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c @@ -100,6 +100,7 @@ #define CAMSV_TG_SEN_GRAB_LIN 0x50C #define CAMSV_TG_PATH_CFG 0x510 +#define IMGO_BASE_ADDR 0x220 #define IMGO_XSIZE 0x230 #define IMGO_YSIZE 0x234 #define IMGO_STRIDE 0x238 @@ -538,6 +539,32 @@ static int mtk_mipicsi_vb2_prepare(struct vb2_buffer *vb) return 0; } +static void mtk_mipicsi_fill_buffer(void __iomem *base, dma_addr_t dma_handle) +{ + writel(dma_handle, base + IMGO_BASE_ADDR); +} + +static void mtk_mipicsi_write_camsv(struct mtk_mipicsi_dev *mipicsi, + unsigned int index, + unsigned int max_camsv_num) +{ + struct mtk_mipicsi_channel *ch = mipicsi->channel; + unsigned int i = 0; + u8 link_index = 0; + u32 bytesperline = mipicsi->fmt.fmt.pix.bytesperline; + u32 height = mipicsi->fmt.fmt.pix.height; + u64 offset = 0; + + for (i = 0; i < max_camsv_num; i++) + if (((mipicsi->link_reg_val >> i) & 0x01) == 0x01) { + offset = (u64)link_index * bytesperline * height; + mtk_mipicsi_fill_buffer(ch[i].camsv, + mipicsi->cam_buf[index].vb_dma_addr_phy + + offset); + link_index++; + } +} + static void mtk_mipicsi_vb2_queue(struct vb2_buffer *vb) { struct mtk_mipicsi_dev *mipicsi = vb2_get_drv_priv(vb->vb2_queue); @@ -546,6 +573,12 @@ static void mtk_mipicsi_vb2_queue(struct vb2_buffer *vb) list_add_tail(&(mipicsi->cam_buf[vb->index].queue), &(mipicsi->fb_list)); spin_unlock(&mipicsi->queue_lock); + + spin_lock(&mipicsi->irqlock); + if (!mipicsi->streamon) + mtk_mipicsi_write_camsv(mipicsi, vb->index, mipicsi->camsv_num); + + spin_unlock(&mipicsi->irqlock); } static void mtk_mipicsi_cmos_vf_enable(struct mtk_mipicsi_dev *mipicsi, @@ -875,6 +908,8 @@ static void mtk_mipicsi_irq_buf_process(struct mtk_mipicsi_dev *mipicsi) ++i; } + mtk_mipicsi_write_camsv(mipicsi, next, mipicsi->camsv_num); + /* * fb_list has one more buffer. Free the first buffer to user * and fill the second buffer to HW. -- 2.18.0