From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F8B8C282CE for ; Tue, 4 Jun 2019 10:12:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4C2BF24C2F for ; Tue, 4 Jun 2019 10:12:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727230AbfFDKMH (ORCPT ); Tue, 4 Jun 2019 06:12:07 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:13010 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727057AbfFDKMH (ORCPT ); Tue, 4 Jun 2019 06:12:07 -0400 X-UUID: 9d690ebe850f417eafe69d94ea59cbf7-20190604 X-UUID: 9d690ebe850f417eafe69d94ea59cbf7-20190604 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 639631439; Tue, 04 Jun 2019 18:12:02 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Jun 2019 18:12:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 4 Jun 2019 18:12:01 +0800 From: Stu Hsieh To: Mauro Carvalho Chehab , Rob Herring , CK Hu CC: Mark Rutland , Matthias Brugger , Stu Hsieh , , , , , , Subject: [PATCH v4 06/14] [media] mtk-mipicsi: enable/disable ana clk Date: Tue, 4 Jun 2019 18:11:47 +0800 Message-ID: <1559643115-15124-7-git-send-email-stu.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1559643115-15124-1-git-send-email-stu.hsieh@mediatek.com> References: <1559643115-15124-1-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch enable/disable ana clk when power on/off Signed-off-by: Stu Hsieh --- .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c index 28dcc683a958..f5cb29077022 100644 --- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c +++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c @@ -182,6 +182,41 @@ static const struct mtk_format mtk_mipicsi_formats[] = { }, }; +static void mtk_mipicsi_ana_clk_enable(void __iomem *base, bool enable) +{ + if (enable) { + writel(1UL | readl(base + MIPI_RX_ANA00_CSI), + base + MIPI_RX_ANA00_CSI); + writel(1UL | readl(base + MIPI_RX_ANA04_CSI), + base + MIPI_RX_ANA04_CSI); + writel(1UL | readl(base + MIPI_RX_ANA08_CSI), + base + MIPI_RX_ANA08_CSI); + writel(1UL | readl(base + MIPI_RX_ANA0C_CSI), + base + MIPI_RX_ANA0C_CSI); + writel(1UL | readl(base + MIPI_RX_ANA10_CSI), + base + MIPI_RX_ANA10_CSI); + writel(1UL | readl(base + MIPI_RX_ANA20_CSI), + base + MIPI_RX_ANA20_CSI); + writel(1UL | readl(base + MIPI_RX_ANA24_CSI), + base + MIPI_RX_ANA24_CSI); + } else { + writel(~1UL & readl(base + MIPI_RX_ANA00_CSI), + base + MIPI_RX_ANA00_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA04_CSI), + base + MIPI_RX_ANA04_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA08_CSI), + base + MIPI_RX_ANA08_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA0C_CSI), + base + MIPI_RX_ANA0C_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA10_CSI), + base + MIPI_RX_ANA10_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA20_CSI), + base + MIPI_RX_ANA20_CSI); + writel(~1UL & readl(base + MIPI_RX_ANA24_CSI), + base + MIPI_RX_ANA24_CSI); + } +} + static void mtk_mipicsi_ana_init(void __iomem *base) { writel(0xFEFBEFBEU & readl(base + MIPI_RX_ANA4C_CSI), @@ -354,6 +389,8 @@ static void mipicsi_clk_enable(struct mtk_mipicsi_dev *mipicsi, bool enable) for (i = 0; i < mipicsi->common_clk_num; i++) enable ? clk_prepare_enable(mipicsi->common_clk[i]) : clk_disable_unprepare(mipicsi->common_clk[i]); + + mtk_mipicsi_ana_clk_enable(mipicsi->ana, enable); } static int mtk_mipicsi_pm_suspend(struct device *dev) -- 2.18.0