From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753630AbdCPVED (ORCPT ); Thu, 16 Mar 2017 17:04:03 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52348 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752744AbdCPVEB (ORCPT ); Thu, 16 Mar 2017 17:04:01 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 93D313B702 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=eric.auger@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 93D313B702 Subject: Re: [RFC PATCH 23/33] irqchip/gic-v3-its: Add VPENDBASER/VPROPBASER accessors To: Marc Zyngier , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu References: <1484648454-21216-1-git-send-email-marc.zyngier@arm.com> <1484648454-21216-24-git-send-email-marc.zyngier@arm.com> Cc: Thomas Gleixner , Jason Cooper , Christoffer Dall From: Auger Eric Message-ID: <155b4430-60ba-66bd-3843-469bb2509ad5@redhat.com> Date: Thu, 16 Mar 2017 22:03:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <1484648454-21216-24-git-send-email-marc.zyngier@arm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Thu, 16 Mar 2017 21:04:01 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 17/01/2017 11:20, Marc Zyngier wrote: > V{PEND,PROP}BASER being 64bit registers, they need some ad-hoc > accessors on 32bit, specially given that VPENDBASER contains > a Valid bit, making the access a bit convoluted. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Eric > --- > arch/arm/include/asm/arch_gicv3.h | 28 ++++++++++++++++++++++++++++ > arch/arm64/include/asm/arch_gicv3.h | 5 +++++ > 2 files changed, 33 insertions(+) > > diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h > index 2747590..3f18832 100644 > --- a/arch/arm/include/asm/arch_gicv3.h > +++ b/arch/arm/include/asm/arch_gicv3.h > @@ -291,5 +291,33 @@ static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr) > */ > #define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c) > > +/* > + * GITS_VPROPBASER - hi and lo bits may be accessed independently. > + */ > +#define gits_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c) > + > +/* > + * GITS_VPENDBASER - the Valid bit must be cleared before changing > + * anything else. > + */ > +static inline void gits_write_vpendbaser(u64 val, void * __iomem addr) > +{ > + u32 tmp; > + > + tmp = readl_relaxed(addr + 4); > + if (tmp & GICR_PENDBASER_Valid) { > + tmp &= ~GICR_PENDBASER_Valid; > + writel_relaxed(tmp, addr + 4); > + } > + > + /* > + * Use the fact that __gic_writeq_nonatomic writes the second > + * half of the 64bit quantity after the first. > + */ > + __gic_writeq_nonatomic(val, addr); > +} > + > +#define gits_read_vpendbaser(c) __gic_readq_nonatomic(c) > + > #endif /* !__ASSEMBLY__ */ > #endif /* !__ASM_ARCH_GICV3_H */ > diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h > index f37e3a2..9420b7a 100644 > --- a/arch/arm64/include/asm/arch_gicv3.h > +++ b/arch/arm64/include/asm/arch_gicv3.h > @@ -188,5 +188,10 @@ static inline void gic_write_bpr1(u32 val) > #define gicr_write_pendbaser(v, c) writeq_relaxed(v, c) > #define gicr_read_pendbaser(c) readq_relaxed(c) > > +#define gits_write_vpropbaser(v, c) writeq_relaxed(v, c) > + > +#define gits_write_vpendbaser(v, c) writeq_relaxed(v, c) > +#define gits_read_vpendbaser(c) readq_relaxed(c) > + > #endif /* __ASSEMBLY__ */ > #endif /* __ASM_ARCH_GICV3_H */ >