From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84027C31E45 for ; Fri, 14 Jun 2019 02:26:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5D3CE21537 for ; Fri, 14 Jun 2019 02:26:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726734AbfFNC0o (ORCPT ); Thu, 13 Jun 2019 22:26:44 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:47019 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726283AbfFNC0n (ORCPT ); Thu, 13 Jun 2019 22:26:43 -0400 X-UUID: c99698b1d3e04bd8a8ead6e2c9b27021-20190614 X-UUID: c99698b1d3e04bd8a8ead6e2c9b27021-20190614 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1399065455; Fri, 14 Jun 2019 10:26:35 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Jun 2019 10:26:34 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 14 Jun 2019 10:26:34 +0800 Message-ID: <1560479194.16718.5.camel@mtksdaap41> Subject: Re: [PATCH v3, 10/27] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case From: CK Hu To: , CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Fri, 14 Jun 2019 10:26:34 +0800 In-Reply-To: <1559734986-7379-11-git-send-email-yongqiang.niu@mediatek.com> References: <1559734986-7379-1-git-send-email-yongqiang.niu@mediatek.com> <1559734986-7379-11-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org +Bibby: Hi, Yongqiang: On Wed, 2019-06-05 at 19:42 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > Here is two modifition in this patch: > 1.bls->dpi0 and rdma1->dsi are differen usecase, > Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase > 2.remove DISP_REG_CONFIG_DPI_SEL setting, DPI_SEL_IN_BLS is 0 and > this is same with hardware defautl setting, > > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 717609d..1bbabe6 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -401,10 +401,9 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs, > } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > config_regs + DISP_REG_CONFIG_OUT_SEL); You move 2 register setting out of the path from BLS to DPI0, does this path still work? Please make sure that all modification could work on all supported SoC. Regards, CK > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > writel_relaxed(DSI_SEL_IN_RDMA, > config_regs + DISP_REG_CONFIG_DSI_SEL); > - writel_relaxed(DPI_SEL_IN_BLS, > - config_regs + DISP_REG_CONFIG_DPI_SEL); > } > } >