From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<tglx@linutronix.de>, <jason@lakedaemon.net>,
<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,
<stefan@agner.ch>, <mark.rutland@arm.com>
Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,
<josephl@nvidia.com>, <talho@nvidia.com>,
<skomatineni@nvidia.com>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <mperttunen@nvidia.com>,
<spatra@nvidia.com>, <robh+dt@kernel.org>, <digetx@gmail.com>,
<devicetree@vger.kernel.org>
Subject: [PATCH V4 08/18] clk: tegra: support for saving and restoring OSC context
Date: Sun, 23 Jun 2019 20:02:49 -0700 [thread overview]
Message-ID: <1561345379-2429-9-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1561345379-2429-1-git-send-email-skomatineni@nvidia.com>
This patch adds support for storing OSC clock frequency and the
drive-strength during OSC clock init and creates an API to restore
OSC control register value from the saved context.
This API is invoked by Tegra210 clock driver during system resume
to restore the OSC clock settings.
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/clk/tegra/clk-tegra-fixed.c | 14 ++++++++++++++
drivers/clk/tegra/clk.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
index 8d91b2b191cf..e8df0ccbffd0 100644
--- a/drivers/clk/tegra/clk-tegra-fixed.c
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -17,7 +17,10 @@
#define OSC_CTRL 0x50
#define OSC_CTRL_OSC_FREQ_SHIFT 28
#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
+#define OSC_CTRL_MASK (0x3f2 | \
+ (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
+static u32 osc_ctrl_ctx;
int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
unsigned long *input_freqs, unsigned int num,
unsigned int clk_m_div, unsigned long *osc_freq,
@@ -29,6 +32,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
unsigned osc_idx;
val = readl_relaxed(clk_base + OSC_CTRL);
+ osc_ctrl_ctx = val & OSC_CTRL_MASK;
osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
if (osc_idx < num)
@@ -96,3 +100,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
*dt_clk = clk;
}
}
+
+void tegra_clk_osc_resume(void __iomem *clk_base)
+{
+ u32 val;
+
+ val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
+ val |= osc_ctrl_ctx;
+ writel_relaxed(val, clk_base + OSC_CTRL);
+ fence_udelay(2, clk_base);
+}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 5ba4f503aea0..5a08827078e4 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -853,6 +853,7 @@ void tegra_cclkg_burst_policy_save_context(void);
void tegra_cclkg_burst_policy_restore_context(void);
void tegra_sclk_cclklp_burst_policy_save_context(void);
void tegra_sclk_cpulp_burst_policy_restore_context(void);
+void tegra_clk_osc_resume(void __iomem *clk_base);
/* Combined read fence with delay */
#define fence_udelay(delay, reg) \
--
2.7.4
next prev parent reply other threads:[~2019-06-24 3:04 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-24 3:02 [PATCH V4 00/18] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 01/18] irqchip: tegra: do not disable COP IRQ during suspend Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 02/18] pinctrl: tegra: add suspend and resume support Sowjanya Komatineni
2019-06-24 9:46 ` Dmitry Osipenko
2019-06-24 17:34 ` Sowjanya Komatineni
2019-06-26 10:08 ` Thierry Reding
2019-06-24 3:02 ` [PATCH V4 03/18] gpio: tegra: use resume_noirq for tegra gpio resume Sowjanya Komatineni
2019-06-25 13:38 ` Linus Walleij
2019-06-26 17:06 ` Sowjanya Komatineni
2019-06-25 13:40 ` Thierry Reding
2019-06-24 3:02 ` [PATCH V4 04/18] clk: tegra: save and restore divider rate Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 05/18] clk: tegra: pllout: save and restore pllout context Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 06/18] clk: tegra: pll: save and restore pll context Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 07/18] clk: tegra: save and restore CPU and System clocks context Sowjanya Komatineni
2019-06-24 3:02 ` Sowjanya Komatineni [this message]
2019-06-24 3:02 ` [PATCH V4 09/18] clk: tegra: add suspend resume support for DFLL Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 10/18] clk: tegra: add save and restore context support for peripheral clocks Sowjanya Komatineni
2019-06-26 10:12 ` Thierry Reding
2019-06-24 3:02 ` [PATCH V4 11/18] clk: tegra210: use fence_udelay during PLLU init Sowjanya Komatineni
2019-06-26 10:12 ` Thierry Reding
2019-06-24 3:02 ` [PATCH V4 12/18] clk: tegra210: support for Tegra210 clocks suspend and resume Sowjanya Komatineni
2019-06-26 10:16 ` Thierry Reding
2019-06-26 16:46 ` Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 13/18] soc/tegra: pmc: allow support for more tegra wake Sowjanya Komatineni
2019-06-24 8:15 ` Marc Zyngier
2019-06-24 16:21 ` Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 14/18] soc/tegra: pmc: add pmc wake support for tegra210 Sowjanya Komatineni
2019-06-26 10:26 ` Thierry Reding
2019-06-26 16:27 ` Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 15/18] arm64: tegra: enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 16/18] soc/tegra: pmc: configure core power request polarity Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 17/18] soc/tegra: pmc: configure deep sleep control settings Sowjanya Komatineni
2019-06-24 3:02 ` [PATCH V4 18/18] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
2019-06-26 10:28 ` Thierry Reding
2019-06-26 16:28 ` Sowjanya Komatineni
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