From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 591D6C76186 for ; Wed, 17 Jul 2019 05:32:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3346220818 for ; Wed, 17 Jul 2019 05:32:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726789AbfGQFcJ (ORCPT ); Wed, 17 Jul 2019 01:32:09 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:32997 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725799AbfGQFcI (ORCPT ); Wed, 17 Jul 2019 01:32:08 -0400 X-UUID: 63807a7f58414eb2859707a1f8ff8aae-20190717 X-UUID: 63807a7f58414eb2859707a1f8ff8aae-20190717 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1883150426; Wed, 17 Jul 2019 13:31:56 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 17 Jul 2019 13:31:54 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 17 Jul 2019 13:31:54 +0800 Message-ID: <1563341514.29169.14.camel@mtksdaap41> Subject: Re: [PATCH v4, 11/33] drm/mediatek: add mutex sof register offset into ddp private data From: CK Hu To: CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Wed, 17 Jul 2019 13:31:54 +0800 In-Reply-To: <1562625253-29254-12-git-send-email-yongqiang.niu@mediatek.com> References: <1562625253-29254-1-git-send-email-yongqiang.niu@mediatek.com> <1562625253-29254-12-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 86CB27915B31E087E11638F66BC5816F7C93AAD27091893D150F28DAAEDA8DA92000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Tue, 2019-07-09 at 06:33 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > mutex sof register offset will be private data of ddp > Reviewed-by: CK Hu > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index ab396ee..d015c1a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -42,12 +42,13 @@ > #define DISP_REG_CONFIG_DPI_SEL 0x064 > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > +#define MT2701_DISP_MUTEX0_SOF0 0x30 > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) > -#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) > +#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) > #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) > > #define INT_MUTEX BIT(1) > @@ -163,6 +164,7 @@ struct mtk_ddp_data { > const unsigned int *mutex_mod; > const unsigned int *mutex_sof; > const unsigned int mutex_mod_reg; > + const unsigned int mutex_sof_reg; > }; > > struct mtk_ddp { > @@ -234,18 +236,21 @@ struct mtk_ddp { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static const struct mtk_ddp_data mt2712_ddp_driver_data = { > .mutex_mod = mt2712_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static const struct mtk_ddp_data mt8173_ddp_driver_data = { > .mutex_mod = mt8173_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, > @@ -527,7 +532,8 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, > } > > writel_relaxed(ddp->data->mutex_sof[sof_id], > - ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); > + ddp->regs + > + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, mutex->id)); > } > > void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > @@ -549,7 +555,8 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, > case DDP_COMPONENT_DPI1: > writel_relaxed(MUTEX_SOF_SINGLE_MODE, > ddp->regs + > - DISP_REG_MUTEX_SOF(mutex->id)); > + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, > + mutex->id)); > break; > default: > if (ddp->data->mutex_mod[id] < 32) {