From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A4DBC76194 for ; Thu, 25 Jul 2019 20:42:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D7969218DA for ; Thu, 25 Jul 2019 20:42:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=crapouillou.net header.i=@crapouillou.net header.b="uAZM9BM/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726687AbfGYUm2 (ORCPT ); Thu, 25 Jul 2019 16:42:28 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:34074 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726195AbfGYUm1 (ORCPT ); Thu, 25 Jul 2019 16:42:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1564087345; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wd/8RY8QtDpKhjy989F9knR8y6y/xiYlDP4O6NQdYHE=; b=uAZM9BM/qI0q0R0385qtFObwkPKHfE1FfrOEybVSU6F4cSubWFYk4SzfU+gQ3oXlhNKr95 GvmdIoBuDI3yn+PA1xHVNwsi/O307s4J6uyrgsXjWp8Rhy4uGzPsB2TeheIxAeR4Y5KaIv GfwfboMFslZNsooUKr5k23NnF0HUVRo= Date: Thu, 25 Jul 2019 16:42:11 -0400 From: Paul Cercueil Subject: Re: [PATCH] MIPS: Add support for partial kernel mode on Xburst CPUs To: Paul Burton Cc: Ralf Baechle , James Hogan , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, od@zcrc.me Message-Id: <1564087331.1848.1@crapouillou.net> In-Reply-To: <20190725165930.yvlvmavcgqocl3nn@pburton-laptop> References: <20190724234654.16555-1-paul@crapouillou.net> <20190725165930.yvlvmavcgqocl3nn@pburton-laptop> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le jeu. 25 juil. 2019 =E0 12:59, Paul Burton a=20 =E9crit : > Hi Paul, >=20 > On Wed, Jul 24, 2019 at 07:46:54PM -0400, Paul Cercueil wrote: >> Support partial kernel mode of Xburst CPUs found in Ingenic SoCs. >> Partial kernel mode means the userspace applications have access to >> the TCSM0 banks of the VPU, >=20 > So far so (reasonably) good :) >=20 >> and can execute cache instructions. >=20 > Aaaah! Scary! >=20 > Does this allow *all* cache instructions? If so that's a big security=20 > & > stability hole - if userland can invalidate kernel data or data from > other programs then it can create all sorts of chaos. It looked a bit fishy to me as well, but I couldn't point a finger to the exact problem. I don't exactly know what it allows and what it doesn't. > Also do you know which Ingenic SoCs this is available on? I see it > documented in the JZ4780 Programming Manual, but Config7 bit 6 is=20 > shown > as reserved in my copy of the XBurst1 CPU Core Programming Manual. I have no idea. I assume all SoCs with a VPU. I know the JZ4770 has it. > I notice the JZ4780 documentation says it allows access "including=20 > TCSM, > CACHE instructions" which is scary too since it doesn't say that's=20 > *all* > it allows access to. Though just cache instructions by themselves are > enough to be game over for any notion of security as mentioned above. >=20 > What is it you want to do with this? I'm wondering if we could achieve > your goal is in a safer way. The plan was to be able to communicate with the firmware running on the VPU without going through expensive context switches all the time. I guess we could mmap() the TCSM memories, but we'd need to bypass the data cache (is there a flag for that?). > Thanks, > Paul =