From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29E5FC76190 for ; Sat, 27 Jul 2019 01:23:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E6C7122C7E for ; Sat, 27 Jul 2019 01:23:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387487AbfG0BXs (ORCPT ); Fri, 26 Jul 2019 21:23:48 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:26686 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2387457AbfG0BXr (ORCPT ); Fri, 26 Jul 2019 21:23:47 -0400 X-UUID: fd71b6eea81b4bb5bce1dbe77ea48a38-20190727 X-UUID: fd71b6eea81b4bb5bce1dbe77ea48a38-20190727 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1997973271; Sat, 27 Jul 2019 09:23:38 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 27 Jul 2019 09:23:34 +0800 Received: from [10.17.3.153] (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sat, 27 Jul 2019 09:23:33 +0800 Message-ID: <1564190613.24702.11.camel@mhfsdcap03> Subject: Re: [PATCH v3 1/2] dt-bindings: i3c: Document MediaTek I3C master bindings From: Qii Wang To: Rob Herring CC: , , , , , , , , , , , Date: Sat, 27 Jul 2019 09:23:33 +0800 In-Reply-To: <20190724202119.GA26566@bogus> References: <1562677762-24067-1-git-send-email-qii.wang@mediatek.com> <1562677762-24067-2-git-send-email-qii.wang@mediatek.com> <20190724202119.GA26566@bogus> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 3115CDD7324A6A0F4379AC19364C2F37546642D4CAA4C5EC9B050BD991421A8C2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2019-07-24 at 14:21 -0600, Rob Herring wrote: > On Tue, Jul 09, 2019 at 09:09:21PM +0800, Qii Wang wrote: > > Document MediaTek I3C master DT bindings. > > > > Signed-off-by: Qii Wang > > --- > > .../devicetree/bindings/i3c/mtk,i3c-master.txt | 48 ++++++++++++++++++++ > > 1 file changed, 48 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt > > > > diff --git a/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt b/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt > > new file mode 100644 > > index 0000000..d32eda6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/i3c/mtk,i3c-master.txt > > @@ -0,0 +1,48 @@ > > +Bindings for MediaTek I3C master block > > +===================================== > > + > > +Required properties: > > +-------------------- > > +- compatible: shall be "mediatek,i3c-master" > > Needs to be SoC specific. > We hope that the SOCs will use the same driver and try to avoid big changes. If there are inevitable changes in the future, then we will modify the compatible to be SoC specific. cdns,i3c-master.txt is not SoC specific either. > > +- reg: physical base address of the controller and apdma base, length of > > + memory mapped region. > > +- reg-names: shall be "main" for master controller and "dma" for apdma. > > +- interrupts: the interrupt line connected to this I3C master. > > +- clocks: shall reference the i3c and apdma clocks. > > +- clock-names: shall include "main" and "dma". > > + > > +Mandatory properties defined by the generic binding (see > > +Documentation/devicetree/bindings/i3c/i3c.txt for more details): > > + > > +- #address-cells: shall be set to 3 > > +- #size-cells: shall be set to 0 > > + > > +Optional properties defined by the generic binding (see > > +Documentation/devicetree/bindings/i3c/i3c.txt for more details): > > + > > +- i2c-scl-hz > > +- i3c-scl-hz > > + > > +I3C device connected on the bus follow the generic description (see > > +Documentation/devicetree/bindings/i3c/i3c.txt for more details). > > + > > +Example: > > + > > + i3c0: i3c@1100d000 { > > + compatible = "mediatek,i3c-master"; > > + reg = <0x1100d000 0x1000>, > > + <0x11000300 0x80>; > > + reg-names = "main", "dma"; > > + interrupts = ; > > + clocks = <&infracfg CLK_INFRA_I3C0>, > > + <&infracfg CLK_INFRA_AP_DMA>; > > + clock-names = "main", "dma"; > > + #address-cells = <3>; > > + #size-cells = <0>; > > + i2c-scl-hz = <100000>; > > + > > + nunchuk: nunchuk@52 { > > + compatible = "nintendo,nunchuk"; > > + reg = <0x52 0x0 0x10>; > > + }; > > + }; > > -- > > 1.7.9.5 > >