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Fri, 9 Aug 2019 17:37:28 +0000 From: "Shirley Her (SC)" To: "adrian.hunter@intel.com" , "ulf.hansson@linaro.org" , "linux-mmc@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: "Chevron Li (WH)" , "Shaper Liu (WH)" , "Xiaoguang Yu (WH)" , "Max Huang (SC)" , "Shirley Her (SC)" Subject: [PATCH V6 1/3] mmc: sdhci: Change O2 Host PLL and DLL register name Thread-Topic: [PATCH V6 1/3] mmc: sdhci: Change O2 Host PLL and DLL register name Thread-Index: AQHVTtkdH7jLrtWrg0qlL9dujbetyg== Date: Fri, 9 Aug 2019 17:37:28 +0000 Message-ID: <1565372245-4598-1-git-send-email-shirley.her@bayhubtech.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR01CA0023.prod.exchangelabs.com (2603:10b6:a02:80::36) To MWHPR16MB1455.namprd16.prod.outlook.com (2603:10b6:320:28::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=shirley.her@bayhubtech.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-originating-ip: [209.36.105.184] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: b36c8144-2f93-42f5-7919-08d71cf03f89 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(7021145)(8989299)(4534185)(7022145)(4603075)(4627221)(201702281549075)(8990200)(7048125)(7024125)(7027125)(7023125)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MWHPR16MB1453; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bayhubtech.com X-MS-Exchange-CrossTenant-Network-Message-Id: b36c8144-2f93-42f5-7919-08d71cf03f89 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Aug 2019 17:37:28.3495 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 0a7aae2b-8f2e-44df-ba2f-42de7f93c642 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7G1XzgtCBjXgd032C/Gj8WLunSK0cH/D0scLUrGwg03onMOcr62eANH6iZA+nUzf+3lL+7ER4QhGyC9qlQ8JukUyIwpnKZ5J05SuhMA/CfA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR16MB1453 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Change register name O2_PLL_WDT_CONTROL1 to O2_PLL_DLL_WDT_CONTROL1 Signed-off-by:Shirley Her --- change in V6: 1. change subject and commit message to match the patch 2. change register name O2_PLL_WDT_CONTROL1 to O2_PLL_DLL_WDT_CONTROL1 change in V5: 1. split 2 patches into 3 patches 2. make dll_adjust_count start from 0 3. fix ret overwritten issue 4. use break instead of goto change in V4: 1. add a bug fix for V3 change in V3: 1. add more explanation in dll_recovery and execute_tuning function 2. move dll_adjust_count to O2_host struct 3. fix some coding style error 4. renaming O2_PLL_WDT_CONTROL1 TO O2_PLL_DLL_WDT_CONTROL1 change in V2: 1. use usleep_range instead of udelay 2. move dll_adjust_count to sdhci-pci-o2micro.c chagne in V1: 1. add error recovery function to relock DLL with correct phase 2. retuning HS200 after DLL locked --- drivers/mmc/host/sdhci-pci-o2micro.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-= pci-o2micro.c index 9dc4548..b3a33d9 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c @@ -51,7 +51,7 @@ #define O2_SD_VENDOR_SETTING2 0x1C8 #define O2_SD_HW_TUNING_DISABLE BIT(4) =20 -#define O2_PLL_WDT_CONTROL1 0x1CC +#define O2_PLL_DLL_WDT_CONTROL1 0x1CC #define O2_PLL_FORCE_ACTIVE BIT(18) #define O2_PLL_LOCK_STATUS BIT(14) #define O2_PLL_SOFT_RESET BIT(12) @@ -316,23 +316,23 @@ static void sdhci_o2_enable_internal_clock(struct sdh= ci_host *host) u32 scratch32; =20 /* PLL software reset */ - scratch32 =3D sdhci_readl(host, O2_PLL_WDT_CONTROL1); + scratch32 =3D sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); scratch32 |=3D O2_PLL_SOFT_RESET; - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); udelay(1); scratch32 &=3D ~(O2_PLL_SOFT_RESET); - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); =20 /* PLL force active */ scratch32 |=3D O2_PLL_FORCE_ACTIVE; - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); =20 /* Wait max 20 ms */ timeout =3D ktime_add_ms(ktime_get(), 20); while (1) { bool timedout =3D ktime_after(ktime_get(), timeout); =20 - scratch =3D sdhci_readw(host, O2_PLL_WDT_CONTROL1); + scratch =3D sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); if (scratch & O2_PLL_LOCK_STATUS) break; if (timedout) { @@ -350,9 +350,9 @@ static void sdhci_o2_enable_internal_clock(struct sdhci= _host *host) =20 out: /* Cancel PLL force active */ - scratch32 =3D sdhci_readl(host, O2_PLL_WDT_CONTROL1); + scratch32 =3D sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); scratch32 &=3D ~O2_PLL_FORCE_ACTIVE; - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); } =20 static int sdhci_o2_get_cd(struct mmc_host *mmc) --=20 2.7.4