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Thu, 15 Aug 2019 16:25:11 +0000 From: "Suthikulpanit, Suravee" To: "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" CC: "pbonzini@redhat.com" , "rkrcmar@redhat.com" , "joro@8bytes.org" , "graf@amazon.com" , "jschoenh@amazon.de" , "karahmed@amazon.de" , "rimasluk@amazon.com" , "Grimm, Jon" , "Suthikulpanit, Suravee" Subject: [PATCH v2 07/15] kvm: x86: svm: Add support to activate/deactivate posted interrupts Thread-Topic: [PATCH v2 07/15] kvm: x86: svm: Add support to activate/deactivate posted interrupts Thread-Index: AQHVU4YCq8MA7E6GfEyia46qTzdwWA== Date: Thu, 15 Aug 2019 16:25:11 +0000 Message-ID: <1565886293-115836-8-git-send-email-suravee.suthikulpanit@amd.com> References: <1565886293-115836-1-git-send-email-suravee.suthikulpanit@amd.com> In-Reply-To: <1565886293-115836-1-git-send-email-suravee.suthikulpanit@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [165.204.78.1] x-clientproxiedby: SN6PR04CA0084.namprd04.prod.outlook.com (2603:10b6:805:f2::25) To DM6PR12MB2844.namprd12.prod.outlook.com (2603:10b6:5:45::32) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; 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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: LSrGPH2vrXg6pgYnbPxxQp3IhPlWIfznewFrZwBWyDIscw9qsQ61IKyQMmzJ2pAAD4en5eIGVFpYdApWdASw8oiRg20W+J/JyZHemINsxlI/OpdValoXBOJWSIa6h8kQwLmuhrcEg6W9nfMo7/16NvECRJgo6C0CYzeVAH0SGd9962unnfcuSsKDLvJmJbybpf96JbwPok8VYOat28audcopxPsOPeVgXImYcGOcKpEe6Vdq8ZZXHnnMYP78m8k3Tyxm7lOAtFvLNneR6uDgIP2Uj6+W3mr8EPmJvcAbqZnfTZ+5386kedf7vb3rcMWQV9Wq+7xmrfa/nPoD0KmtOi/IgleNSbFlALkGHQwjiu30u7nqByMPFMhI2lX6iwLWlW1tqjqnlt0gmzR/VLxfldOVYnrPybgve+b76kYSdms= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 967724da-82f3-4994-355f-08d7219d2531 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Aug 2019 16:25:11.5937 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Q9b+YKTndgz28RxMG+4P8wq7BB4p7g0OQUG/Woa5edcS/NUIe4GJXkMpdHSBWpY+RckBDD48EA1T6wXvZoNn6Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3897 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce interface for activate/deactivate posted interrupts, and implement SVM hooks to toggle AMD IOMMU guest virtual APIC mode. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/kvm_host.h | 4 ++++ arch/x86/kvm/svm.c | 44 +++++++++++++++++++++++++++++++++++++= ++++ arch/x86/kvm/x86.c | 6 ++++++ 3 files changed, 54 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index dfb7c3d..0d8544b 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1183,6 +1183,10 @@ struct kvm_x86_ops { =20 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, bool set); + + int (*activate_pi_irte)(struct kvm_vcpu *vcpu); + int (*deactivate_pi_irte)(struct kvm_vcpu *vcpu); + void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); =20 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 6851bce..b674cd0 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -5374,6 +5374,48 @@ static int svm_update_pi_irte(struct kvm *kvm, unsig= ned int host_irq, return ret; } =20 +static int svm_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) +{ + int ret =3D 0; + unsigned long flags; + struct amd_svm_iommu_ir *ir; + struct vcpu_svm *svm =3D to_svm(vcpu); + + if (!kvm_arch_has_assigned_device(vcpu->kvm)) + return 0; + + /* + * Here, we go through the per-vcpu ir_list to update all existing + * interrupt remapping table entry targeting this vcpu. + */ + spin_lock_irqsave(&svm->ir_list_lock, flags); + + if (list_empty(&svm->ir_list)) + goto out; + + list_for_each_entry(ir, &svm->ir_list, node) { + if (activate) + ret =3D amd_iommu_activate_guest_mode(ir->data); + else + ret =3D amd_iommu_deactivate_guest_mode(ir->data); + if (ret) + break; + } +out: + spin_unlock_irqrestore(&svm->ir_list_lock, flags); + return ret; +} + +static int svm_activate_pi_irte(struct kvm_vcpu *vcpu) +{ + return svm_set_pi_irte_mode(vcpu, true); +} + +static int svm_deactivate_pi_irte(struct kvm_vcpu *vcpu) +{ + return svm_set_pi_irte_mode(vcpu, false); +} + static int svm_nmi_allowed(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); @@ -7269,6 +7311,8 @@ static bool svm_need_emulation_on_page_fault(struct k= vm_vcpu *vcpu) .pmu_ops =3D &amd_pmu_ops, .deliver_posted_interrupt =3D svm_deliver_avic_intr, .update_pi_irte =3D svm_update_pi_irte, + .activate_pi_irte =3D svm_activate_pi_irte, + .deactivate_pi_irte =3D svm_deactivate_pi_irte, .setup_mce =3D svm_setup_mce, =20 .smi_allowed =3D svm_smi_allowed, diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 40a20bf..5ab1643 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -7177,6 +7177,9 @@ void kvm_vcpu_activate_apicv(struct kvm_vcpu *vcpu) kvm_apic_update_apicv(vcpu); =20 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); + + if (kvm_x86_ops->activate_pi_irte) + kvm_x86_ops->activate_pi_irte(vcpu); } EXPORT_SYMBOL_GPL(kvm_vcpu_activate_apicv); =20 @@ -7192,6 +7195,9 @@ void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) vcpu->arch.apicv_active =3D false; kvm_apic_update_apicv(vcpu); =20 + if (kvm_x86_ops->deactivate_pi_irte) + kvm_x86_ops->deactivate_pi_irte(vcpu); + kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); } EXPORT_SYMBOL_GPL(kvm_vcpu_deactivate_apicv); --=20 1.8.3.1