From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EF10C3A5A4 for ; Wed, 28 Aug 2019 12:29:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2639E22CED for ; Wed, 28 Aug 2019 12:29:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726607AbfH1M3D (ORCPT ); Wed, 28 Aug 2019 08:29:03 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:63063 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726428AbfH1M3A (ORCPT ); Wed, 28 Aug 2019 08:29:00 -0400 X-UUID: 07e4afb7c74a4584920a1462ee7269f2-20190828 X-UUID: 07e4afb7c74a4584920a1462ee7269f2-20190828 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 844402232; Wed, 28 Aug 2019 20:28:53 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 28 Aug 2019 20:28:59 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 28 Aug 2019 20:28:59 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd , Ryan Case CC: Nicolas Boichat , Fan Chen , James Liao , Weiyi Lu , , , , , Henry Chen Subject: [PATCH V3 10/10] arm64: dts: mt8183: Add interconnect provider DT nodes Date: Wed, 28 Aug 2019 20:28:48 +0800 Message-ID: <1566995328-15158-11-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566995328-15158-1-git-send-email-henryc.chen@mediatek.com> References: <1566995328-15158-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 5A7D628ED1EE4F9C2C551AEC390E7608E055E3BDF0690A1F4EA55F66C15079B52000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DDR EMI provider dictating dram interconnect bus performance found on MT8183-based platforms Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 7512f84..a3af77d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -11,6 +11,7 @@ #include #include "mt8183-pinfunc.h" #include +#include / { compatible = "mediatek,mt8183"; @@ -148,6 +149,10 @@ reg = <0 0x10012000 0 0x1000>; clocks = <&infracfg CLK_INFRA_DVFSRC>; clock-names = "dvfsrc"; + ddr_emi: interconnect { + compatible = "mediatek,mt8183-emi"; + #interconnect-cells = <1>; + }; }; timer { -- 1.9.1