From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4DD4C3A5A5 for ; Tue, 3 Sep 2019 07:06:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7FBB222DCC for ; Tue, 3 Sep 2019 07:06:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727005AbfICHG1 (ORCPT ); Tue, 3 Sep 2019 03:06:27 -0400 Received: from mail-sh.amlogic.com ([58.32.228.43]:19737 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725895AbfICHG1 (ORCPT ); Tue, 3 Sep 2019 03:06:27 -0400 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Tue, 03 Sep 2019 03:06:26 EDT Received: from droid13.amlogic.com (116.236.93.172) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Tue, 3 Sep 2019 14:52:13 +0800 From: Jianxin Pan To: Kevin Hilman , CC: Jianxin Pan , Rob Herring , Carlo Caione , Neil Armstrong , Jerome Brunet , Martin Blumenstingl , , , , Jian Hu , Hanjie Lin , Xingyu Chen , Victor Wan , Qiufang Dai , Tao Zeng Subject: [PATCH 0/4] arm64: Add basic support for Amlogic A1 SoC Family Date: Tue, 3 Sep 2019 02:51:11 -0400 Message-ID: <1567493475-75451-1-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [116.236.93.172] Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A1 is an application processor designed for smart audio and IoT applications, with Dual core ARM Cortex-A35 CPU. Unlike the previous GXL and G12 series, there is no Cortex-M3 AO CPU in it. This serial add basic support for the Amlogic A1 based Amlogic AD401 board: which describe components as follows: Reserve Memory, CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. The pclk for uart_AO_B need to be fixed once A1 clock driver is merged. In this version, it rely on bootloader to enable the pclk gate Jianxin Pan (4): soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs dt-bindings: arm: amlogic: add A1 bindings dt-bindings: arm: amlogic: add Amlogic AD401 bindings arm64: dts: add support for A1 based Amlogic AD401 Documentation/devicetree/bindings/arm/amlogic.yaml | 6 + arch/arm64/boot/dts/amlogic/Makefile | 1 + arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 +++++ arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 121 +++++++++++++++++++++ drivers/soc/amlogic/meson-gx-socinfo.c | 2 + 5 files changed, 160 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-a1.dtsi -- 2.7.4