From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEADFC432C2 for ; Wed, 25 Sep 2019 11:59:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A352921D7E for ; Wed, 25 Sep 2019 11:59:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405150AbfIYL7y (ORCPT ); Wed, 25 Sep 2019 07:59:54 -0400 Received: from mail-sz.amlogic.com ([211.162.65.117]:37247 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727145AbfIYL7x (ORCPT ); Wed, 25 Sep 2019 07:59:53 -0400 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Wed, 25 Sep 2019 07:59:52 EDT Received: from droid15-sz.amlogic.com (10.28.8.25) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.1591.10; Wed, 25 Sep 2019 19:44:49 +0800 From: Jian Hu To: Jerome Brunet , Neil Armstrong CC: Jian Hu , Kevin Hilman , Rob Herring , Martin Blumenstingl , Michael Turquette , Stephen Boyd , Qiufang Dai , Jianxin Pan , , , , , Subject: [PATCH 0/2] add Amlogic A1 clock controller driver Date: Wed, 25 Sep 2019 19:44:46 +0800 Message-ID: <1569411888-98116-1-git-send-email-jian.hu@amlogic.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.28.8.25] Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org add support for Amlogic A1 clock driver, the clock includes three parts: peripheral clocks, pll clocks, CPU clocks. sys pll and CPU clocks will be sent in next patch. Unlike the previous series, there is no EE/AO domain in A1 clock controllers. Jian Hu (2): dt-bindings: clock: meson: add A1 clock controller bindings clk: meson: a1: add support for Amlogic A1 clock driver .../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 65 + arch/arm64/Kconfig.platforms | 1 + drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a1.c | 2617 ++++++++++++++++++++ drivers/clk/meson/a1.h | 172 ++ include/dt-bindings/clock/a1-clkc.h | 102 + 7 files changed, 2968 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml create mode 100644 drivers/clk/meson/a1.c create mode 100644 drivers/clk/meson/a1.h create mode 100644 include/dt-bindings/clock/a1-clkc.h -- 1.9.1