From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04147ECE58D for ; Wed, 9 Oct 2019 09:18:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DB7A0206C0 for ; Wed, 9 Oct 2019 09:18:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730059AbfJIJSD (ORCPT ); Wed, 9 Oct 2019 05:18:03 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:29520 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725914AbfJIJSC (ORCPT ); Wed, 9 Oct 2019 05:18:02 -0400 X-UUID: d81f63e11cfb47dab81b2162cf116290-20191009 X-UUID: d81f63e11cfb47dab81b2162cf116290-20191009 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1963904463; Wed, 09 Oct 2019 17:10:16 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 17:10:12 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Oct 2019 17:10:11 +0800 Message-ID: <1570612214.3420.1.camel@mtksdaap41> Subject: Re: [PATCH v5, 14/32] drm/mediatek: add ddp component CCORR From: CK Hu To: CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Wed, 9 Oct 2019 17:10:14 +0800 In-Reply-To: <1567090254-15566-15-git-send-email-yongqiang.niu@mediatek.com> References: <1567090254-15566-1-git-send-email-yongqiang.niu@mediatek.com> <1567090254-15566-15-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 0375CF6B4E5FA8BAAEA7F23CA35E102C5801DCA5C075E2664B67D2C2A9BE51702000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > This patch add ddp component CCORR > Applied to mediatek-drm-next-5.5 [1], thanks. [1] https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5 Regards, CK > Signed-off-by: Yongqiang Niu > Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32 +++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++ > 2 files changed, 34 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index d1afa06..b18bd66 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -33,6 +33,12 @@ > #define DISP_AAL_EN 0x0000 > #define DISP_AAL_SIZE 0x0030 > > +#define DISP_CCORR_EN 0x0000 > +#define CCORR_EN BIT(0) > +#define DISP_CCORR_CFG 0x0020 > +#define CCORR_RELAY_MODE BIT(0) > +#define DISP_CCORR_SIZE 0x0030 > + > #define DISP_GAMMA_EN 0x0000 > #define DISP_GAMMA_CFG 0x0020 > #define DISP_GAMMA_SIZE 0x0030 > @@ -123,6 +129,24 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp) > writel_relaxed(0x0, comp->regs + DISP_AAL_EN); > } > > +static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc) > +{ > + writel(h << 16 | w, comp->regs + DISP_CCORR_SIZE); > + writel(CCORR_RELAY_MODE, comp->regs + DISP_CCORR_CFG); > +} > + > +static void mtk_ccorr_start(struct mtk_ddp_comp *comp) > +{ > + writel(CCORR_EN, comp->regs + DISP_CCORR_EN); > +} > + > +static void mtk_ccorr_stop(struct mtk_ddp_comp *comp) > +{ > + writel_relaxed(0x0, comp->regs + DISP_CCORR_EN); > +} > + > static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc) > @@ -171,6 +195,12 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, > .stop = mtk_aal_stop, > }; > > +static const struct mtk_ddp_comp_funcs ddp_ccorr = { > + .config = mtk_ccorr_config, > + .start = mtk_ccorr_start, > + .stop = mtk_ccorr_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_gamma = { > .gamma_set = mtk_gamma_set, > .config = mtk_gamma_config, > @@ -192,6 +222,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, > [MTK_DISP_RDMA] = "rdma", > [MTK_DISP_WDMA] = "wdma", > [MTK_DISP_COLOR] = "color", > + [MTK_DISP_CCORR] = "ccorr", > [MTK_DISP_AAL] = "aal", > [MTK_DISP_GAMMA] = "gamma", > [MTK_DISP_UFOE] = "ufoe", > @@ -213,6 +244,7 @@ struct mtk_ddp_comp_match { > [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, > [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index 108de60..8d220224 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -20,6 +20,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_RDMA, > MTK_DISP_WDMA, > MTK_DISP_COLOR, > + MTK_DISP_CCORR, > MTK_DISP_AAL, > MTK_DISP_GAMMA, > MTK_DISP_UFOE, > @@ -36,6 +37,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_AAL0, > DDP_COMPONENT_AAL1, > DDP_COMPONENT_BLS, > + DDP_COMPONENT_CCORR, > DDP_COMPONENT_COLOR0, > DDP_COMPONENT_COLOR1, > DDP_COMPONENT_DPI0,