From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9466ECE58D for ; Wed, 9 Oct 2019 09:36:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8B67420673 for ; Wed, 9 Oct 2019 09:36:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730330AbfJIJgX (ORCPT ); Wed, 9 Oct 2019 05:36:23 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:9585 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725942AbfJIJgW (ORCPT ); Wed, 9 Oct 2019 05:36:22 -0400 X-UUID: c19fab52b8bb4fd4a6fb7bf723bf0a0c-20191009 X-UUID: c19fab52b8bb4fd4a6fb7bf723bf0a0c-20191009 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1108232262; Wed, 09 Oct 2019 17:36:01 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 17:35:59 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Oct 2019 17:35:59 +0800 Message-ID: <1570613761.7713.15.camel@mtksdaap41> Subject: Re: [PATCH v5, 24/32] drm/mediatek: add clock property check before get it From: CK Hu To: CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Wed, 9 Oct 2019 17:36:01 +0800 In-Reply-To: <1567090254-15566-25-git-send-email-yongqiang.niu@mediatek.com> References: <1567090254-15566-1-git-send-email-yongqiang.niu@mediatek.com> <1567090254-15566-25-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 245755396B82B8B6F48F7B8E82316EBB41F1B194122EA2DF61C4B744C093FDBA2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > This patch add clock property check before get it > I've rewrite this patch and applied to mediatek-drm-next-5.5 [1] with the title "drm/mediatek: add no_clk into ddp private data", thanks. [1] https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5 Regards, CK > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index a5a6689..effc24a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -657,10 +657,12 @@ static int mtk_ddp_probe(struct platform_device *pdev) > for (i = 0; i < 10; i++) > ddp->mutex[i].id = i; > > - ddp->clk = devm_clk_get(dev, NULL); > - if (IS_ERR(ddp->clk)) { > - dev_err(dev, "Failed to get clock\n"); > - return PTR_ERR(ddp->clk); > + if (of_find_property(dev->of_node, "clocks", &i)) { > + ddp->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(ddp->clk)) { > + dev_err(dev, "Failed to get clock\n"); > + return PTR_ERR(ddp->clk); > + } > } > > regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);